IP Library › Granted Patent US 10,497,709
Granted Patent B2
US 10,497,709 · App. 16/019,064 · Granted Dec 3, 2019

Semiconductor memory device

Inventors: Mikiko Mori (Kuwana, JP); Ryota Suzuki (Yokkaichi, JP); Tatsuya Kato (Yokkaichi, JP); Wataru Sakamoto (Yokkaichi, JP); Fumie Kikushima (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11556H01L27/11524H01L27/11529
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Quick Facts
Patent No.
US 10,497,709
App. No.
16/019,064
Granted
Dec 3, 2019
Kind
B2
Abstract

A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a contact connected to the connection member. There is not a conductive member disposed between the two semiconductor pillars.

Claims (65)

1. A semiconductor memory device comprising:

a substrate;

a first signal line extending in a first direction;

a second signal line extending in the first direction, the first signal line and the second signal line being arranged in a second direction intersecting the first direction;

a first insulating layer being arranged between the first signal line and the second signal line, the insulating layer extending in the first direction;

a first electrode film extending in a third direction intersecting the first direction and the second direction;

a second electrode film extending in the third direction, the first electrode film and the second electrode film being arranged in the second direction;

a first memory cell between the first signal line and the first electrode film to store first information;

a second memory cell between the second signal line and the second electrode film to store second information;

a first connection member including a first portion and a second portion, the first portion being electrically connected in common to an upper portion of the first signal line and an upper portion of the second signal line, the second portion being arranged between the first signal line and the second signal line and being connected in the first insulating layer;

a first contact being electrically connected to the first portion; and

a first interconnect extending in the second direction and electrically connected to the first contact.

2. The device according to claim 1 , wherein

a first side surface of the first signal line connected to the second portion and a second side surface of the second signal line connected to the second portion.

3. The device according to claim 1 , wherein

the first signal line and the second signal line are disposed between the first electrode film and the second electrode film.

4. The device according to claim 1 , wherein the first electrode film and the second electrode film are not disposed between the first signal line and the second signal line.

5. The device according to claim 1 , further comprising:

a conductive layer being electrically connected in common to a lower portion of the first signal line and a lower portion of the second signal line.

6. The device according to claim 1 , further comprising:

a conductive layer being provided above the substrate,

wherein the first signal line and the second signal line are provided above the surface of the conductive layer and lower ends of at least one of the first signal line and the second signal line are in contact with a recessed portion formed on the surface of the conductive layer.

7. The device according to claim 1 , wherein

a lower portion of the first signal line and a lower portion of the second signal line are integrated together.

8. The device according to claim 1 , further comprising:

a third signal line extending in the first direction, the first signal line and the third signal line being arranged in the third direction;

a fourth signal line extending in the first direction, the second signal line and the fourth signal line being arranged in the third direction, the third signal line and the fourth signal line being arranged in the second direction;

a second insulating layer being arranged between the third signal line and the fourth signal line, the insulating layer extending in the first direction;

a third memory cell provided between the third signal line and the first electrode film;

a fourth memory cell portion provided between the fourth signal line and the second electrode film;

a second connection member including a third portion and a fourth portion, the third portion being electrically connected in common to an upper portion of the third signal line and an upper portion of the fourth signal line, the fourth portion being arranged between the third signal line and the second signal line and being connected in the second insulating layer being connected in common to an upper portion of the third signal line and an upper portion of the fourth signal line;

a second contact being electrically connected to the third portion; and

a second interconnect extending in the second direction and electrically connected to the second contact.

9. A semiconductor memory device comprising:

a substrate;

a first signal line extending in a first direction;

a second signal line extending in the first direction, the first signal line and the second signal line being arranged in a second direction intersecting the first direction, an upper part of an area between the first signal line and the second signal line being filled with a conductive material and a lower part of the area between the first signal line and the second signal line being filled with an insulating material;

a first electrode film extending in a third direction intersecting the first direction and the second direction;

a second electrode film extending in the third direction, the first electrode film and the second electrode film being arranged in the second direction;

a first memory cell between the first signal line and the first electrode film to store first information;

a second memory cell between the second signal line and the second electrode film to store second information;

a first connection member being electrically connected in common to an upper portion of the first signal line and an upper portion of the second signal line;

a first contact being electrically connected to the first connection member; and

a first interconnect extending in the second direction and electrically connected to the first contact.

10. The device according to claim 9 , wherein the conductive material contacts with the first connection member.

11. The device according to claim 9 , wherein the conductive material in the upper part of the area and the first connection member include a same material.

12. The device according to claim 9 , wherein

the first signal line and the second signal line are disposed between the first electrode film and the second electrode film in the second direction.

13. The device according to claim 9 , wherein the first electrode film and the second electrode film are not disposed between the first signal line and the second signal line.

14. The device according to claim 9 , further comprising:

a conductive layer being electrically connected in common to a lower portion of the first signal line and a lower portion of the second signal line.

15. The device according to claim 9 , further comprising:

a conductive layer, forming a recessed portion, being provided above the substrate,

wherein the first signal line and the second signal line are provided above the surface of the conductive layer and a lower end of at least one of the first signal line and the second signal line is in contact with the recessed portion formed on the surface of the conductive layer.

16. The device according to claim 9 , wherein

a lower portion of the first signal line and a lower portion of the second signal line are integrated with each other.

17. The device according to claim 9 , further comprising:

a third signal line extending in the first direction, the first signal line and the third signal line being arranged in the third direction;

a fourth signal line extending in the first direction, the second signal line and the fourth signal line being arranged in the third direction, the third signal line and the fourth signal line being arranged in the second direction, an upper part of a second area between the third signal line and the fourth signal line being filled with a second conductive material and a lower part of the second area between the third signal line and the fourth signal line being filled with a second insulating material;

a third memory cell provided between the third signal line and the first electrode film;

a fourth memory cell provided between the fourth signal line and the second electrode film;

a second connection member being electrically connected in common to an upper portion of the third signal line and an upper portion of the fourth signal line;

a second contact being electrically connected to the second connection member; and

a second interconnect extending in the second direction and electrically connected to the second contact.

18. The device according to claim 9 , wherein the conductive material is in contact with the side surfaces of the first signal line and the second signal line.

Assignments (3)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
Continuity (5)
Continuation 15674135 · Aug 10, 2017
Continuation 15269061 · Sep 19, 2016
Continuation 14644542 · Mar 11, 2015
Provisional Application 62049104 · Sep 11, 2014
Related Publication 20180323204A1 · Nov 8, 2018