3D semiconductor memory device and structure
A semiconductor memory, including: a first memory cell including a first transistor; a second memory cell including a second transistor; and a memory peripherals transistor, the memory peripherals transistor is overlaying the second transistor or is underneath the first transistor, where the second memory cell overlays the first memory cell at a distance of less than 200 nm, and where the memory peripherals transistor is part of a peripherals circuit controlling the memory.
1. A semiconductor memory, comprising:
a first memory cell comprising a first transistor;
a second memory cell comprising a second transistor;
a memory peripherals transistor, said memory peripherals transistor is atop said second transistor,
wherein said second memory cell is above said first memory cell at a distance of less than 200 nm,
wherein said memory peripherals transistor is part of a peripherals circuit controlling said memory, and
wherein said second memory cell and said first memory cell have been processed following the same lithography step and accordingly are self-aligned; and
a copper-based connection layer disposed between said memory peripherals transistor and said second memory cell.
2. The semiconductor memory according to claim 1 ,
wherein said second transistor comprises a single crystal channel.
3. The semiconductor memory according to claim 1 ,
wherein said first transistor is a polysilicon transistor.
4. The semiconductor memory according to claim 1 ,
wherein said first transistor is a junction-less transistor.
5. The semiconductor memory according to claim 1 , further comprising:
an isolation layer disposed between said memory peripherals transistor and said first transistor.
6. The semiconductor memory according to claim 1 ,
wherein said memory peripherals transistor comprises a single crystal channel.
7. The semiconductor memory according to claim 1 further comprising:
an isolation layer disposed between said memory peripherals transistor and said first transistor,
wherein said isolation layer comprises a via having a radius of less than 400 nm.