Semiconductor power device
A semiconductor power device includes an n-type drift layer, a plurality of first p-doped regions, a plurality of n-doped regions, a plurality of second p-doped regions, a gate dielectric layer, a gate electrode, an interlayer dielectric layer and a plurality of source contacts. Each first p-doped region includes a first p-doped portion and a plurality of first p-doped arms extending outwards from the first p-doped portion. Each n-doped region includes an n-doped portion and a plurality of n-doped arms extending outwards from the n-doped portion.
1. A semiconductor power device, comprising;
an n-type drift layer;
a plurality of first p-doped regions disposed at the n-type drift layer, each of the plurality of first p-doped regions comprising a first p-doped center portion and a plurality of first p-doped extending portions extending outwards from the first p-doped center portion in a Y-axis direction;
a plurality of n-doped regions disposed in the plurality of first p-doped regions, each of the plurality of n-doped regions center comprising an n-doped portion corresponding to the first p-doped center portion and a plurality of n-doped extending portions extending outwards from the n-doped center portion corresponding to the plurality of first p-doped extending portions in the Y-axis direction;
a plurality of second p-doped regions adjacent to the first p-doped center portion;
a gate dielectric layer disposed on the n-type drift layer;
a gate electrode disposed on the gate dielectric layer;
an interlayer dielectric layer disposed on the gate dielectric layer and the gate electrode; and
a plurality of source contacts, each of the plurality of source contacts passing through the interlayer dielectric layer and the gate dielectric layer to form an Ohmic contact with a part of the n-doped portion and the plurality of second p-doped center regions.
2. The semiconductor power device of claim 1 , wherein the n-type drift layer is made of silicon carbide.
3. The semiconductor power device of claim 1 , wherein each of the plurality of first p-doped extending portions comprises a pair of first arms and a pair of second arms extending towards a direction opposite the first arms, and the first arm of any of the plurality of first p-doped extending portions is connected to the second arm of the adjacent first p-doped extending portions.
4. The semiconductor power device of claim 3 , wherein each of the plurality of n-doped arms comprises a pair of first arms and a pair of second arms extending towards a direction opposite the first arms, and the first arm of any of the plurality of n-doped arms is connected to the second arm of the adjacent n-doped arm.
5. The semiconductor power device of claim 1 , wherein each of the plurality of first p-doped arms comprises a pair of first arms and a pair of second arins extending towards a direction opposite the first aims, and the first arm of any of the plurality of first p-doped aims is separated from the second arm of the adjacent p-doped arm.
6. The semiconductor power device of claim 5 , wherein each of the plurality of n-doped arms comprises a pair of first arms and a pair of second arms extending towards a direction opposite the first arms, and the first arm of any of the plurality of n-doped arms is separated from the second arm of the adjacent n-doped arm.
7. The semiconductor power device of claim 1 , wherein each of the plurality of first p-doped arms comprises a plurality of first arms extending along a first direction of an axis and a plurality of second arms extending along a second direction of the axis, and the plurality of first arms of any of the plurality of first p-doped arms are separated from the plurality of second arms of the adjacent first p-doped arm.
8. The semiconductor power device of claim 7 , wherein each of the plurality of n-doped arms comprises a plurality of first arms extending along a first direction of an axis and a plurality of second arms extending along a second direction of the axis, and the plurality of first arms of any of the plurality of n-doped arms are separated from the plurality of second arms of the adjacent n-doped arm.
9. The semiconductor power device of claim 1 , wherein each of the plurality of first p-doped arms comprises a pair of first arms extending along a first direction of an axis, and a connecting atm connecting between the first arms.
10. The semiconductor power device of claim 9 , wherein each of the plurality of n-doped arms comprises a pair of first arms extending along a first direction of an axis and a connecting arm connecting between the first anus.
11. The semiconductor power device of claim 1 , wherein a channel is formed between an outer boundary of each of the plurality of first p-doped region and an outer boundary of each of the plurality of n-doped region, and the channel comprise a length L ch between 0.1 μm and 2 μm.
12. The semiconductor power device of claim 1 , wherein the n-type drift layer has a doping concentration not less than 1E14 cm −3 .
13. The semiconductor power device of claim 1 , wherein the n-drift layer comprises an upper portion and a lower portion, and the upper portion has a thickness greater than 0.1 μm and has a doping concentration lower than 1E18 cm −3 and higher than that of the lower portion.
14. The semiconductor power device of claim 1 , wherein the plurality of first p-doped regions have a doping concentration between 1E16 cm −3 and 1E19 cm −3 , and the plurality of n-doped regions have a doping concentration between 1E19 cm −3 and 1E21 cm −3 , and the plurality of second p-doped regions have a doping concentration between 1E18 cm −3 and 1E21 cm −3 .
15. The semiconductor power device of claim 1 , configured as a metal-oxide semiconductor field-effect oxide (MOSFET) or an insulated gate bipolar transistor (IGBT).