FinFET structures and methods of forming the same
A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.
1. A method comprising:
forming a first semiconductor fin protruding from a substrate;
forming a gate stack over the first semiconductor fin, wherein forming the gate stack comprises:
depositing a gate dielectric layer over the first semiconductor fin;
depositing a first seed layer over the gate dielectric layer;
depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer; and
depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer comprise the same conductive material; and
forming source and drain regions adjacent the gate stack.
2. The method of claim 1 , wherein the first seed layer has a crystalline structure and the second seed layer has an amorphous structure.
3. The method of claim 1 , wherein the conductive material is tungsten.
4. The method of claim 1 , wherein forming the gate stack comprises:
depositing a capping layer over the gate dielectric layer; and
etching back the capping layer, wherein remaining portions of the capping layer have edges lower than a top surface of the gate dielectric layer.
5. The method of claim 4 , wherein forming the gate stack comprises:
depositing a work-function layer over the capping layer and the gate dielectric layer; and
depositing a barrier layer over the work-function layer.
6. The method of claim 1 , wherein the first seed layer is deposited using a first deposition process and the second seed layer is deposited using a second deposition process that is different than the first deposition process.
7. A method comprising:
forming a dummy gate stack on a semiconductor region;
forming gate spacers on sidewalls of the dummy gate stack;
removing the dummy gate stack to form an opening;
forming a gate dielectric layer extending into the opening;
forming a seed layer over the gate dielectric layer extending into the opening, wherein forming the seed layer comprises:
depositing a first seed sublayer using a first deposition process; and
depositing a second seed sublayer over the first seed sublayer using a second deposition process; and
filling the remaining opening with a conductive material.
8. The method of claim 7 , wherein the first deposition process deposits a crystalline material and wherein the second deposition process deposits an amorphous material.
9. The method of claim 7 , wherein depositing the first seed sublayer using the first deposition process comprises using WCl 5 as a precursor material.
10. The method of claim 7 , wherein depositing the second seed sublayer using the second deposition process comprises using WF 6 as a precursor material.
11. The method of claim 7 , wherein forming a seed layer further comprises depositing a third seed sublayer over the second seed sublayer using a third deposition process.
12. The method of claim 11 , wherein the third deposition process deposits a crystalline material.
13. The method of claim 7 , wherein the first deposition process comprises chemical vapor deposition (CVD).
14. A method of forming a semiconductor device comprising:
forming a semiconductor fin over a substrate, the semiconductor fin comprising a channel region;
forming a gate stack over the channel region, wherein forming the gate stack comprises:
forming a dielectric material over the channel region;
forming a seed layer over the dielectric material, wherein forming the seed layer comprises forming a plurality of sublayers, wherein at least one sublayer is crystalline and at least one sublayer is amorphous; and
forming a conductive material over the seed layer; and
forming source/drain regions adjacent to opposite sides of the channel region.
15. The method of claim 14 , further comprising forming the gate stack over sidewalls of the fin and over a top surface of the fin.
16. The method of claim 14 , wherein forming the seed layer comprises forming a first amorphous sublayer over a first crystalline sublayer.
17. The method of claim 16 , wherein forming the seed layer comprises forming a second crystalline sublayer over the first amorphous sublayer.
18. The method of claim 14 , wherein the plurality of sublayers of the seed layer comprise tungsten.
19. The method of claim 14 , wherein forming the gate stack further comprises forming a barrier layer over the dielectric layer.
20. The method of claim 14 , wherein a first lateral cross-section of the conductive material has a smaller area than a second lateral cross-section of the conductive material, wherein the second lateral cross-section is farther from the channel region than the first lateral cross-section.