Two-phase three-level converter and controller therefor
View Patent ↗Disclosed are multilevel buck converters, and controllers and methods for operating such converters. Embodiments improve the voltage gain (V o /V in ) of multi-level DC-DC converters, such as three-level converters, that is imposed by a duty cycle limitation in conventional approaches. According to certain embodiments, the duty cycle of switches is controlled to so that the converter output voltage is increased.
1. A two-phase asymmetrical three-level buck converter, comprising:
a first input terminal connected to a first common terminal of a first switch connected in parallel with a third switch;
a first node connected to a second common terminal of the first and third switches, and to a first common terminal of a second switch connected in parallel with a fourth switch;
a second common terminal of the second and fourth switches connected to a second node and a first terminal of a fifth switch;
a first capacitor having a first terminal connected to the first node and a second terminal connected to a third node and a first terminal of a sixth switch;
a first inductor having a first terminal connected to the second node and a second terminal connected to a main output terminal;
a second inductor having a first terminal connected to the third node and a second terminal connected to the main output terminal;
a common node connected to a second input terminal, a second terminal of the sixth switch, a second terminal of the fifth switch, and a second output terminal;
a second capacitor connected between the main output terminal and the second output terminal; and
a controller that provides a driving signal for each of the first to sixth switches so that the first, second, third, and fourth switches are turned on and off once, sequentially, during one switching cycle and the fifth switch and the sixth switch are each turned on and off twice during one switching cycle.
2. The two-phase asymmetrical three-level buck converter of claim 1 , comprising:
a DC power supply connected across the first input terminal and the second input terminal.
3. The two-phase asymmetrical three-level buck converter of claim 1 , wherein the controller drives the first to sixth switches so that:
the first, second, third, and fourth switches are driven with 90° phase difference from each other;
the fifth switch is driven complementarily to the second and fourth switches; and
the sixth switch is driven complementarily to the first and third switches.
4. The two-phase asymmetrical three-level buck converter of claim 1 , wherein the controller drives the first to sixth switches so that:
the first, second, third, and fourth switches are turned on and off once, sequentially, during one switching cycle, wherein a duty cycle of each of the first to fourth switches is prolonged such that successive on times of the first, second, third, and fourth switches overlap by a selected interval; and
the fifth switch and the sixth switch are each turned on and off twice during a switching cycle;
wherein the fifth and sixth switches are off during the overlaps of the on times of the first to fourth switches.
5. A controller for a two-phase asymmetrical three-level buck converter, comprising:
an input that receives a signal corresponding to the converter output voltage or current;
a circuit that generates a duty cycle signal based on the sensed output voltage or current;
a driving circuit that generates gate drive signals for switches of the converter;
wherein the converter is the two-phase asymmetrical three-level buck converter of claim 1 ;
wherein the controller drives the first to sixth switches so that:
the first, second, third, and fourth switches are turned on and off once, sequentially, during one switching cycle, wherein a duty cycle of each of the first to fourth switches is prolonged such that successive on times of the first, second, third, and fourth switches overlap by a selected interval; and
the fifth switch and the sixth switch are each turned on and off twice during a switching cycle;
wherein the fifth and sixth switches are off during the overlaps of the on times of the first to fourth switches.
6. The controller of claim 5 , wherein increasing the selected interval of the overlap of the successive on times of the first to fourth switches increases the output voltage of the two-phase asymmetrical three-level buck converter.
7. A controller for a series capacitor buck converter comprising first and second control switches and first and second synchronous rectifier (SR) switches, the controller comprising:
an input that receives a signal corresponding to the converter output voltage or current;
a circuit that generates a duty cycle signal based on the sensed output voltage or current;
a driving circuit that generates gate drive signals for switches of the converter;
wherein the controller drives the switches so that:
the first and second control switches are turned on and off once, sequentially, during one switching cycle, wherein a duty cycle of each of the first and second control switches is greater than 50% such that the on times of the first and second control switches overlap by a selected interval; and
the first and second SR switches are each turned on and off once, sequentially, during a switching cycle, wherein each of the on times of the first and second SR switches coincides with an off time of one of the first and second control switches;
wherein the first and second SR switches are off during the overlaps of the on times of the first and second control switches.
8. The controller of claim 7 , wherein increasing the duty cycle above 50% increases the output voltage of the series capacitor buck converter.
9. A method for controlling a series capacitor buck converter comprising first and second control switches and first and second synchronous rectifier (SR) switches, comprising controlling the switches so that:
the first and second control switches are turned on and off once, sequentially, during one switching cycle, wherein a duty cycle of each of the first and second control switches is greater than 50% such that the on times of the first and second control switches overlap by a selected interval; and
the first and second SR switches are each turned on and off once, sequentially, during a switching cycle, wherein each of the on times of the first and second SR switches coincides with an off time of one of the first and second control switches;
wherein the first and second SR switches are off during the overlaps of the on times of the first and second control switches.
10. A series capacitor buck converter comprising the controller of claim 7 .
11. A method for controlling the two-phase asymmetrical three-level buck converter of claim 1 , comprising controlling the first to sixth switches so that:
the first, second, third, and fourth switches are turned on and off once, sequentially, during one switching cycle, wherein a duty cycle of each of the first to fourth switches is prolonged such that successive on times of the first, second, third, and fourth switches overlap by a selected interval; and
the fifth switch and the sixth switch are each turned on and off twice during a switching cycle;
wherein the fifth and sixth switches are off during the overlaps of the on times of the first to fourth switches.
12. The method of claim 11 , wherein increasing the selected interval of the overlap of the successive on times of the first to fourth switches increases an output voltage of the two-phase asymmetrical three-level buck converter.
13. The method of claim 9 , wherein increasing the duty cycle above 50% increases an output voltage of the series capacitor buck converter.