Multi-nyquist zone digital-to-analog converter (DAC)
A multi-zone digital-to-analog device is provided with a digital-to-analog (D/A) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), a clock input to accept a clock signal with a clock frequency of P Hz, and an output to supply an analog value having a bandwidth of M Hz. An upsampling stage has an input to accept the analog value and a clock input to accept the clock signal. The upsampling stage has a device bandwidth of L Hz to supply an analog output signal with a full power bandwidth of K Hz, where (P/2)=M and M<K<L. The upsampling stage supplies analog output signal images in a plurality of Nyquist zones. In one aspect, the D/A stage supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.
1. A multi-Nyquist zone digital-to-analog device comprising:
a first semiconductor substrate with a digital-to-analog (DIA) stage having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), and an output to supply an analog value having a bandwidth of M Hz; and,
a second semiconductor substrate with an upsampling stage having an input to accept the analog value, and an output to supply an analog output signal in a Qth Nyquist zone, where Q is an integer greater than 1 and each Nyquist zone has a bandwidth of M Hz.
2. The multi-Nyquist zone digital-to-analog device of claim 1 wherein the D/A stage further comprises a clock input to accept a first clock signal with a frequency of P Hz, and supplies N deinterleaved analog values having a combined bandwidth of M Hz, where N×(P/2)=M.
3. The multi-Nyquist zone digital-to-analog device of claim 1 wherein the upsampling stage supplies analog output signal images in a plurality of Nyquist zones within a full power bandwidth of K Hz.
4. The multi-Nyquist zone digital-to-analog device of claim 2 wherein the D/A stage further comprises:
N packaging interfaces respectively connecting the analog values from the D/A stage output to the upsampling stage input, each packaging interface having a bandwidth of less than M Hz.
5. The multi-Nyquist zone digital-to-analog device of claim 1 wherein the upsampling stage has a device bandwidth of L Hz and a full power bandwidth of K Hz, where M<K<L.
6. The multi-Nyquist zone digital-to-analog device of claim 2 wherein the upsampling stage has a clock input to accept a second clock signal, having a frequency of P Hz, for interleaving the N deinterleaved analog values.
7. The multi-Nyquist zone digital-to-analog device of claim 6 wherein the D/A stage comprises:
a deinterleaver having a signal input to accept the digital input signal, a clock input to accept the first clock signal, and an output to supply N deinterleaved digital values;
a bank of N digital-to-analog converters (DACs), each DAC having a signal input to accept a corresponding deinterleaved digital value, a clock input to accept the second clock signal, and a signal output to supply a corresponding deinterleaved analog value;
wherein the upsampling stage comprises:
a bank of N first sample-and-hold (S/H) circuits, each first S/H circuit having an input to accept a corresponding deinterleaved analog value, a control port to accept the second clock signal, and an output to supply a corresponding sampled analog value;
a delay-locked loop having an input to accept the second clock signal, and an output to supply the N phases of the clock frequency;
a bank of N current impulse (CI) DACs, each CI DAC having an input to accept a corresponding sampled analog value, a control port to accept the second clock signal, and an output to supply a corresponding impulse signal;
a bank of N second S/H circuits, each second S/H circuit having an input to accept a corresponding impulse signal, a control port to accept a corresponding second clock phase, and an output to supply a corresponding sampled impulse signal; and,
an interleaver having an input to accept the N sampled impulse signals and an output to supply the analog output signal.
8. The multi-Nyquist zone digital-to-analog device of claim 7 wherein the D/A stage DACs are zero-order hold DACs supplying analog values having a pulse width duration of 1/P; and,
wherein the CI DACs supply impulse signals having a root mean square (RMS) pulse width duration of less than or equal to 1/(N×P).
9. The multi-Nyquist zone digital-to-analog device of claim 1 further comprising:
a bandpass selectable filter having an input to accept the analog output signal and an output to supply a bandpass-filtered analog output signal in a predetermined Nyquist zone.
10. A multi-Nyquist zone digital-to-analog device comprising:
the digital-to-analog device having an input to accept a digital input signal with a data bandwidth of M Hertz (Hz), and an output to supply an analog output signal in a Qth Nyquist zone, where Q is an integer greater than 1 and each Nyquist zone has a bandwidth of M Hz.
11. The multi-Nyquist zone digital-to-analog device of claim 10 wherein the input accepts N deinterleaved digital input signals having a combined bandwidth of M Hz.
12. The multi-Nyquist zone digital-to-analog device of claim 11 wherein the digital-to analog device further comprises a clock input to accept a clock signal with a frequency of P Hz, where N×(P/2)=M.
13. The multi-Nyquist zone digital-to-analog device of claim 10 wherein the digital-to-analog device has a device bandwidth of L Hz and the output supplies an analog output signal with a full power bandwidth of K Hz, where 3M<K<L.
14. The multi-Nyquist zone digital-to-analog device of claim 10 wherein the analog output signal includes signal images in a plurality of Nyquist zones within a full power bandwidth of K Hz.
15. The multi-Nyquist zone digital-to-analog device of claim 12 further comprising:
a bank of N first sample-and-hold (S/H) circuits, each first S/H circuit having a signal input to accept a corresponding deinterleaved digital value, a clock input, and a signal output to supply a corresponding sampled analog value;
a delay-locked loop having an input to accept the clock signal, and an output to supply N phases of the clock frequency;
a bank of N current impulse (CI) digital-to-analog converters (DACs), each CI DAC having an input to accept a corresponding sampled analog value, a control port to accept the clock signal, and an output to supply a corresponding impulse signal;
a bank of N second S/H circuits, each second S/H circuit having an input to accept a corresponding impulse signal, a control port to accept a corresponding clock phase, and an output to supply a corresponding sampled impulse signal; and,
an interleaver having an input to accept the N sampled impulse signals and an output to supply the analog output signal.
16. The multi-Nyquist zone digital-to-analog device of claim 15 wherein the CI DACs supply impulse signals having a root mean square (RMS) pulse width duration of less than or equal to 1/(N×P).
17. The multi-Nyquist zone digital-to-analog device of claim 10 further comprising:
a bandpass filter having an input to accept the analog output signal, and an output to supply a filtered signal with a bandwidth of M Hz in a predetermined Nyquist zone.
18. A method for multi-Nyquist zone digital-to-analog conversion, the method comprising:
a digital-to-analog (DIA) stage accepting a digital input signal with a data bandwidth of M Hertz (Hz);
the D/A stage converting the digital signal to an analog value having a bandwidth of M Hz; and,
an upsampler stage sampling the analog value to supply an analog output signal in a Qth Nyquist zone, where Q is an integer greater than 1 and each Nyquist zone has a bandwidth of M Hz.
19. The method of claim 18 further comprising:
the D/A stage sampling the digital signal to create N deinterleaved digital values; and,
wherein converting the digital signal includes converting the N deinterleaved digital values to N deinterleaved analog values having a combined bandwidth of M Hz,
wherein sampling the analog value comprises:
processing the N deinterleaved analog values through a bank of N current impulse (CI) DACs at a rate of P Hz; and,
interleaving the N impulse signals to supply the analog output signal.
20. The method of claim 18 wherein sampling the analog value includes supplying analog output signal images in a plurality of Nyquist zones within a full power bandwidth of K Hz.