Dynamic adjustment of operating conditions of integrated circuits
Apparatuses and Methods for dynamic adjustment of operating conditions of integrated circuits are provided. The method includes receiving, from a voltage reference module, an operating voltage of the integrated circuit, receiving a reference clock to be used as an operating frequency of the integrated circuit and is distributed to by the plurality of circuit blocks in the integrated circuit, measuring feedback path timing information of one or more circuit blocks in the plurality of circuit blocks, comparing the feedback path timing information of the one or more circuit blocks to the reference clock, determining timing margins of corresponding one or more feedback paths of the one or more circuit blocks based on the comparison, and generating a feedback for adjusting the operating voltage or the operating frequency of the integrated circuit based on the timing margins of the one or more feedback paths of the one or more circuit blocks.
1. A method of dynamically adjusting an operating conditions of an integrated circuit, comprising:
receiving, from a voltage reference module, an operating voltage of the integrated circuit, wherein the operating voltage is distributed in a power grid that drives a plurality of circuit blocks of the integrated circuit;
receiving, from a clock generator, a reference clock, wherein the reference clock is used as an operating frequency of the integrated circuit and is distributed to by the plurality of circuit blocks in the integrated circuit;
measuring, by a circuit performance monitor, feedback path timing information of one or more circuit blocks in the plurality of circuit blocks, wherein the circuit performance monitor includes one or more replica feedback paths corresponding to one or more feedback paths in the one or more circuit blocks, and wherein the feedback path timing information includes feedback path delay data of the one or more replica feedback paths;
comparing, by a performance adjuster, the feedback path timing information of the one or more circuit blocks to the reference clock;
determining timing margins of corresponding one or more feedback paths of the one or more circuit blocks based on the comparison; and
generating, by the performance adjuster, a feedback for adjusting the operating voltage or the operating frequency of the integrated circuit based on the timing margins of the one or more feedback paths of the one or more circuit blocks.
2. The method of claim 1 , further comprising:
receiving, from the voltage reference module, an updated operating voltage, wherein the updated operating voltage is generated in accordance with the feedback provided by the performance adjuster; and
distributing the updated operating voltage to the plurality of circuit blocks of the integrated circuit through the power grid.
3. The method of claim 1 , further comprising:
providing, by an on-die regulator, the operating voltage of the integrated circuit to the power grid;
receiving, at the on-die regulator, the feedback for adjusting the operating voltage; and
generating, by the on-die regulator, an updated operating voltage using the operating voltage of the integrated circuit from the voltage reference module and the feedback received from the performance adjuster, wherein the updated operating voltage is distributed to the plurality of circuit blocks of the integrated circuit through the power grid.
4. The method of claim 1 , wherein
the one or more feedback paths are identified based on static timing analysis of the integrated circuit; and
for each feedback path in the one or more feedback paths, a replica feedback path is created near the feedback path with same circuit components and with same path length between the same circuit components.
5. The method of claim 1 , wherein comparing the feedback path timing information of the one or more circuit blocks to the reference clock comprises:
selecting, by a multiplexer, a feedback path from the one or more feedback paths; and
providing, by the multiplexer, a feedback path delay data, a corresponding data mask and a clock of the feedback path selected.
6. The method of claim 5 , further comprising:
receiving, by a phase sampler, the feedback path delay data and the corresponding data mask of the feedback path selected; and
generating, by the phase sampler, indications of increment and indications of decrement using the feedback path delay data, the corresponding data mask and the clock of the feedback path selected.
7. The method of claim 6 , wherein the phase sampler is operated according to a feedback path data sampling window identified based on at least one of:
a period when a corresponding feedback path data mask is asserted; or
a trigger configured to indicate a period of measured performance data being sampled, wherein the trigger is generated based on a state of the feedback path or the trigger is generated to create a toggle of a launching flip flop of the feedback path based on a state of the launching flip flop.
8. The method of claim 6 , further comprising:
counting, by a counter, the indications of increment and the indication of decrement generated by the phase sampler;
providing, by the counter, a number of fine bits that represent the indications of increment and the indications of decrement generated by the phase sampler; and
providing, by the counter, a number of coarse bits, wherein each coarse bit in the number of coarse bits represent s a predetermined set of fine bits.
9. The method of claim 8 , further comprising:
storing, in a fine-bits register, the number of fine bits provided by the counter;
storing, in a coarse-bits register, the number of coarse bits provided by the counter;
generating, by a summation unit, a sum of the fine bits and course bits; and
generating, by a digital to analog converter, the feedback for adjusting the operating voltage based on the sum of the fine bits and course bits.
10. An integrated circuit with dynamically adjustable operating conditions, comprising:
a power grid configured to receive an operating voltage of the integrated circuit from a voltage reference module, wherein the operating voltage is distributed to drive a plurality of circuit blocks of the integrated circuit;
a clock generator configured to receive a reference clock, wherein the reference clock is used as an operating frequency of the integrated circuit and is distributed to by the plurality of circuit blocks in the integrated circuit;
a circuit performance monitor configured to measure feedback path timing information of one or more circuit blocks in the plurality of circuit blocks, wherein the circuit performance monitor includes one or more replica feedback paths corresponding to one or more feedback paths in the one or more circuit blocks, and wherein the feedback path timing information includes feedback path delay data of the one or more replica feedback paths; and
a performance adjuster configured to compare the feedback path timing information of the one or more circuit blocks to the reference clock, determine timing margins of corresponding one or more feedback paths of the one or more circuit blocks based on the comparison, and generate a feedback for adjusting the operating voltage or the operating frequency of the integrated circuit based on the timing margins of the one or more feedback paths of the one or more circuit blocks.
11. The integrated circuit of claim 10 , wherein the power grid is further configured to:
receive, from the voltage reference module, an updated operating voltage, wherein the updated operating voltage is generated in accordance with the feedback provided by the performance adjuster; and
distribute the updated operating voltage to the plurality of circuit blocks of the integrated circuit through the power grid.
12. The integrated circuit of claim 10 , further comprises an on-die regulator configured to:
provide the operating voltage of the integrated circuit to the power grid;
receive the feedback for adjusting the operating voltage; and
generate an updated operating voltage using the operating voltage of the integrated circuit from the voltage reference module and the feedback received from the performance adjuster, wherein the updated operating voltage is distributed to the plurality of circuit blocks of the integrated circuit through the power grid.
13. The integrated circuit of claim 10 , wherein
the one or more feedback paths are identified based on static timing analysis of the integrated circuit; and
for each feedback path in the one or more feedback paths, a replica feedback path is created near the feedback path with same circuit components and with same path length between the same circuit components.
14. The integrated circuit of claim 10 , wherein the performance adjuster comprises a multiplexer configured to:
select a feedback path from the one or more feedback paths; and
provide a feedback path delay data, a corresponding data mask and a clock of the feedback path selected.
15. The integrated circuit of claim 14 , wherein the performance adjuster further comprises a phase sampler configured to:
receive the feedback path delay data, the corresponding data mask and the clock of the feedback path selected; and
generate indications of increment and indications of decrement using the feedback path delay data, the corresponding data mask and the clock of the feedback path selected.
16. The integrated circuit of claim 15 , wherein the phase sampler is operated according to a feedback path data sampling window identified based on at least one of:
a period when a corresponding feedback path data mask is asserted; or
a trigger configured to indicate a period of measured performance data being sampled, wherein the trigger is generated based on a state of the feedback path or the trigger is generated to create a toggle of a launching flip flop of the feedback path based on a state of the launching flip flop.
17. The integrated circuit of claim 15 , wherein the performance adjuster further comprises a counter configured to:
count the indications of increment and the indication of decrement generated by the phase sampler;
provide a number of fine bits that represent the indications of increment and the indications of decrement generated by the phase sampler; and
provide a number of coarse bits, wherein each coarse bit in the number of coarse bits represent s a predetermined set of fine bits.
18. The integrated circuit of claim 17 , wherein the performance adjuster further comprises:
a fine-bits register configured to store the number of fine bits provided by the counter;
a coarse-bits register configured to store the number of coarse bits provided by the counter;
a summation unit configured to generate a sum of the fine bits and course bits; and a digital to analog converter configured to generate the feedback for adjusting the operating voltage based on the sum of the fine bits and course bits.