IP Library › Granted Patent US 10,504,894
Granted Patent B2
US 10,504,894 · App. 15/370,463 · Granted Dec 10, 2019

Semiconductor device

Inventors: Seung Hyun Song (Hwaseong-si, KR); Yoon Suk Kim (Hwaseong-si, KR); Kyu Baik Chang (Seoul, KR); Ui Hui Kwon (Hwaseong-si, KR); Yo Han Kim (Seoul, KR); Jong Chol Kim (Seoul, KR); Chang Wook Jeong (Hwaseong-si, KR)
Assignee: Samsung Electronics Co., Ltd.
H01L27/0886H01L27/0207H01L27/0924H01L29/0649H01L29/785H01L21/823431H01L21/823437H01L21/823481H01L21/823821H01L21/823828H01L21/823878
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Quick Facts
Patent No.
US 10,504,894
App. No.
15/370,463
Granted
Dec 10, 2019
Kind
B2
Abstract

A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

Claims (54)

1. A semiconductor device, comprising:

a fin-type pattern extending in a first direction;

a device isolation film surrounding the fin-type pattern and exposing an upper portion of the fin-type pattern;

a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction;

a gate isolation film isolating portions of the gate electrode in the second direction, and comprising a first material; and

on the device isolation film, an interlayer insulating film on a side surface of the gate electrode and comprising a second material different from the first material,

wherein a stress characteristic of the gate isolation film is different from a stress characteristic of the interlayer insulating film, and

wherein the gate isolation film has a compressive stress characteristic, and the interlayer insulating film has a tensile stress characteristic.

2. The semiconductor device of claim 1 , wherein the fin-type pattern comprises a first fin-type pattern and a second fin-type pattern spaced apart from each other in the second direction, and

the gate isolation film is between the first and second fin-type patterns, and extends in the first direction.

3. The semiconductor device of claim 1 , wherein the gate electrode comprises first to third gate electrodes spaced apart from one another in the first direction, and

the gate isolation film isolates the second gate electrode without contacting the first and third gate electrodes.

4. The semiconductor device of claim 1 , further comprising a first trench within the device isolation film in the first direction, and isolating portions of the gate electrode in the second direction, wherein the gate isolation film fills the first trench.

5. The semiconductor device of claim 4 , wherein the gate isolation film comprises:

an outer gate isolation film conformally on a bottom surface and a side surface of the first trench, and

an inner gate isolation film on the outer gate isolation film, entirely filling the first trench.

6. The semiconductor device of claim 1 , wherein the gate isolation film comprises first and second gate isolation films spaced apart from each other in the second direction, and

the fin-type pattern is between the first and second gate isolation films.

7. The semiconductor device of claim 6 , further comprising:

a second trench between the fin-type pattern and the first gate isolation film, and

a third gate isolation film in the second trench.

8. A semiconductor device, comprising:

a first gate electrode extending in a first direction;

a first gate isolation film isolating portions of the first gate electrode, and extending in a second direction intersecting the first direction;

a second gate isolation film isolating portions of the first gate electrode, extending in the second direction, and being spaced apart from the first gate isolation film in the first direction;

a first active region between the first and second gate isolation films; and

a third gate isolation film between the first active region and the first gate isolation film,

wherein the first and third gate isolation films being without an active region between the first and third gate isolation films.

9. The semiconductor device of claim 8 , wherein a length of the third gate isolation film in the second direction is shorter than a length of the first gate isolation film in the second direction.

10. The semiconductor device of claim 8 , further comprising a first interlayer insulating film on a side surface of the first gate electrode and comprising a first material.

11. The semiconductor device of claim 8 , further comprising second and third gate electrodes extending in the first direction and being positioned on opposite sides of the first gate electrode, respectively,

wherein the first gate isolation film isolates portions of the second and third gate electrodes.

12. The semiconductor device of claim 11 , further comprising:

a fin-type pattern protruding on a substrate, and extending in the second direction, and

a device isolation film surrounding a portion of a side surface of the fin-type pattern,

wherein the first to third gate electrodes are on the device isolation film and the fin-type pattern.

13. The semiconductor device of claim 11 , further comprising at least one fourth gate isolation film between the first active region and the second gate isolation film,

wherein the second and fourth gate isolation films being without an active region between the second and fourth gate isolation films.

14. The semiconductor device of claim 11 , wherein the third gate isolation film isolates portions of the first and third gate electrodes, and further comprises:

a first interlayer insulating film on side surfaces of the first to third gate electrodes, respectively,

a second interlayer insulating film on the first to third gate electrodes, the first interlayer insulating film, and the first to third gate isolation films, and

a first connect pattern passing through the second interlayer insulating film and electrically re-connecting the third gate electrode which is isolated by the third gate isolation film.

15. The semiconductor device of claim 11 , wherein the third gate isolation film isolates portions of the first gate electrode without isolating portions of the second and third gate electrodes.

16. The semiconductor device of claim 15 , further comprising, between the first and second gate isolation films, a fourth gate isolation film isolating portions of the second gate electrode without isolating portions the first and third gate electrodes, and

between the first and second gate isolation films, a fifth gate isolation film isolating portions of the third gate electrode without isolating portions of the first and second gate electrodes.

17. The semiconductor device of claim 16 , further comprising a first interlayer insulating film on side surfaces of the first to third gate electrodes, respectively,

a second interlayer insulating film on the first to third gate electrodes, the first interlayer insulating film, and the first to fifth gate isolation films, and

a first connect pattern passing through the second interlayer insulating film and electrically re-connecting the first gate electrode which is isolated by the third gate isolation film.

18. A semiconductor device, comprising:

first and second gate electrodes extending in parallel with each other in a first direction, and being spaced apart from each other in a second direction intersecting the first direction;

a first gate isolation film extending in the second direction, isolating portions of the first gate electrode in the first direction, and isolating portions of the second gate electrode in the first direction;

a second gate isolation film extending in the second direction, isolating portions of the first gate electrode in the first direction, isolating portions of the second gate electrode in the first direction, and being spaced apart from the first gate isolation film in the first direction;

a third gate isolation film extending in the second direction, isolating portions of the first gate electrode in the first direction, and being between the first and second gate isolation films; and

a fourth gate isolation film extending in the second direction, isolating portions of the second gate electrode in the first direction, being between the first and second gate isolation films, and being entirely spaced apart from the third gate isolation film in the first direction and in the second direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2016
From: SONG, SEUNG HYUN; KIM, YOON SUK; CHANG, KYU BAIK; KWON, UI HUI; KIM, YO HAN; KIM, JONG CHOL; JEONG, CHANG WOOK
To: SAMSUNG ELECTRONICS CO.,LTD.
Reel/Frame 040583/0757 →
Priority Claims (1)
KR 10-2015-0173134 · Dec 7, 2015 · national
Continuity (1)
Related Publication 20170162568A1 · Jun 8, 2017