Integrated circuit with resurf region biasing under buried insulator layers
Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.
1. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a first region along the surface, the first region having a first conductivity type;
an insulator layer abutting the first region;
a second region abutting the insulator layer, the second region having a second conductivity type opposite to the first conductivity type;
a conductive path extending from the surface, through the insulator layer and into the second region;
a trench structure extending from the surface and reaching the insulator layer, the trench structure encircling the first region;
the semiconductor substrate has the first conductivity type; and
the second region includes a buried doped region having the second conductivity type.
2. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a first region along the surface, the first region having a first conductivity type;
an insulator layer abutting the first region;
a second region abutting the insulator layer, the second region having a second conductivity type opposite to the first conductivity type;
a conductive path extending from the surface, through the insulator layer and into the second region;
a trench structure extending from the surface and reaching the insulator layer, the trench structure encircling the first region;
the semiconductor substrate has the second conductivity type; and
the second region includes a buried doped region having a higher doping concentration than the semiconductor substrate.
3. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a first region along the surface, the first region having a first conductivity type;
an insulator layer abutting the first region;
a second region abutting the insulator layer, the second region having a second conductivity type opposite to the first conductivity type;
a conductive path extending from the surface, through the insulator layer and into the second region;
a trench structure extending from the surface and reaching the insulator layer, the trench structure encircling the first region;
the semiconductor substrate has the second conductivity type; and
the second region includes a same doping concentration as the semiconductor substrate.
4. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a first region along the surface, the first region having a first conductivity type;
an insulator layer abutting the first region;
a second region abutting the insulator layer, the second region having a second conductivity type opposite to the first conductivity type;
a conductive path extending from the surface, through the insulator layer and into the second region;
a trench structure extending from the surface and reaching the insulator layer, the trench structure encircling the first region;
a bipolar transistor having:
a collector layer in the first region, the collector layer having the first conductivity type;
a base layer above the collector layer, the base layer having the second conductivity type; and
an emitter layer above the base layer, the emitter layer having the first conductivity type.
5. An integrated circuit comprising:
a semiconductor substrate having a surface;
a bipolar transistor having collector region under and near the surface, the collector region having a first conductivity type;
an insulator layer abutting the collector region;
a doped region abutting the insulator layer, the doped region having a second conductivity type opposite to the first conductivity type;
a conductive path extending from the surface, through the insulator layer and into the doped region; and
a trench structure extending from the surface and reaching the insulator layer, the trench structure encircling the collector region and insulating the collector region from the conductive path, wherein:
the first conductivity type includes a p-type;
the second conductivity type includes an n-type; and
the conductive path includes an n-type poly-silicon plug.
6. The integrated circuit of claim 5 , further comprising:
a first terminal for receiving a first voltage supply (GND);
a second terminal for receiving a second voltage supply (VCC) higher than the first voltage supply (GND), the second terminal coupled to the n-type poly-silicon plug.
7. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a bipolar transistor having collector region under and near the surface, the collector region having a first conductivity type;
an insulator layer abutting the collector region;
a doped region abutting the insulator layer, the doped region having a second conductivity type opposite to the first conductivity type;
a conductive path extending from the surface, through the insulator layer and into the doped region; and
a trench structure extending from the surface and reaching the insulator layer, the trench structure encircling the collector region and insulating the collector region from the conductive path, wherein:
the first conductivity type includes an n-type;
the second conductivity type includes a p-type; and
the conductive path includes a p-type poly-silicon plug and a p-type contact region interfacing the second end with the doped region.
8. The integrated circuit of claim 7 , further comprising:
a first terminal for receiving a first voltage supply (VCC);
a second terminal for receiving a second voltage supply (GND) lower than the first voltage supply (VCC), the second terminal coupled to the p-type poly-silicon plug.
9. An integrated circuit, comprising:
a semiconductor substrate having a surface;
a first transistor having a first p-type region under and near the surface;
a second transistor having a first n-type region under and near the surface;
an insulator layer directly under the first p-type region and the first n-type region;
a second n-type region under the insulator layer and overlapping the first p-type region;
a second p-type region under the insulator layer and overlapping the first n-type region;
an n-type poly-silicon plug extending from the surface and penetrating the insulator layer to reach the second n-type region; and
a p-type poly-silicon plug extending from the surface and penetrating the insulator layer to reach the second p-type region.
10. The integrated circuit of claim 9 , further comprising:
a first trench structure extending from the surface and reaching the insulator layer, the first trench structure positioned between the first p-type region and the n-type poly-silicon plug; and
a second trench structure extending from the surface and reaching the insulator layer, the second trench structure positioned between the first n-type region and the p-type poly-silicon plug.
11. The integrated circuit of claim 9 , further comprising:
a first trench structure extending from the surface and reaching the insulator layer, the first trench structure separately encircling the first p-type region and the n-type poly-silicon plug; and
a second trench structure extending from the surface and reaching the insulator layer, the second trench structure separately encircling the first n-type region and the p-type poly-silicon plug.
12. The integrated circuit of claim 9 , further comprising:
a first terminal configured to receive a first voltage supply (VCC), the first terminal coupled to the n-type poly-silicon plug;
a second terminal configured to receive a second voltage supply (GND) lower than the first voltage supply (VCC), the second terminal coupled to the p-type poly-silicon plug.
13. A method of making an integrated circuit, comprising:
providing a semiconductor substrate having a surface;
providing a first transistor having a first p-type region under and near the surface;
providing a second transistor having a first n-type region under and near the surface;
providing an insulator layer directly under the first p-type region and the first n-type region;
providing a second n-type region under the insulator layer and overlapping the first p-type region;
providing a second p-type region under the insulator layer and overlapping the first n-type region;
providing an n-type poly-silicon plug extending from the surface and penetrating the insulator layer to reach the second n-type region; and
providing a p-type poly-silicon plug extending from the surface and penetrating the insulator layer to reach the second p-type region.
14. The method of claim 13 , further comprising:
providing a first trench structure extending from the surface and reaching the insulator layer, the first trench structure positioned between the first p-type region and the n-type poly-silicon plug; and
providing a second trench structure extending from the surface and reaching the insulator layer, the second trench structure positioned between the first n-type region and the p-type poly-silicon plug.
15. The method of claim 13 , further comprising:
providing a first trench structure extending from the surface and reaching the insulator layer, the first trench structure separately encircling the first p-type region and the n-type poly-silicon plug; and
providing a second trench structure extending from the surface and reaching the insulator layer, the second trench structure separately encircling the first n-type region and the p-type poly-silicon plug.
16. The method of claim 13 , further comprising:
providing a first terminal configured to receive a first voltage supply (VCC), the first terminal coupled to the n-type poly-silicon plug;
providing a second terminal configured to receive a second voltage supply (GND) lower than the first voltage supply (VCC), the second terminal coupled to the p-type poly-silicon plug.