IP Library › Granted Patent US 10,504,997
Granted Patent B2
US 10,504,997 · App. 15/613,977 · Granted Dec 10, 2019

Silicon-germanium Fin structure having silicon-rich outer surface

Inventors: Hemanth Jagannathan (Niskayuna, NY); ChoongHyun Lee (Rensselaer, NY); Shogo Mochizuki (Clifton Park, NY); Koji Watanabe (Rensselaer, NY)
Assignee: International Business Machines Corporation
H01L29/165H01L21/0217H01L21/02271H01L21/324H01L21/762H01L27/0886H01L29/1037H01L29/1041H01L29/1054H01L29/66795H01L29/66818H01L29/785
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Quick Facts
Patent No.
US 10,504,997
App. No.
15/613,977
Granted
Dec 10, 2019
Kind
B2
Abstract

A semiconductor structure includes a substrate and a silicon-germanium (SiGe) fin formed on the substrate. The SiGe fin has a first portion having a first doping profile and a second portion having a second doping profile. The first portion of the SiGe fin has a Si-rich outer surface.

Claims (28)

1. A semiconductor structure comprising:

a substrate;

a silicon-germanium (SiGe) fin disposed on the substrate and comprising a first portion and a second portion, wherein the second portion is disposed on the substrate and the first portion is disposed on the second portion; and

a first oxide layer disposed on the substrate and up to a top surface of the second portion of the SiGe fin and a silicon nitride layer disposed on the substrate and along the first oxide layer,

wherein outer surfaces of sidewalls and a top surface of the first portion of the SiGe fin are Si-rich outer surfaces.

2. The semiconductor structure of claim 1 , wherein the Si-rich outer surface is formed from an oxide layer comprising a mixture of a germanium oxide compound and a silicon oxide compound.

3. The semiconductor structure of claim 2 , wherein the germanium oxide compound is GeO 2 .

4. The semiconductor structure of claim 2 , wherein the silicon oxide compound is SiO 2 .

5. The semiconductor structure of claim 2 , wherein the silicon oxide compound is silicon dioxide (SiO 2 ) and the germanium oxide compound is germanium dioxide (GeO 2 ).

6. The semiconductor structure of claim 1 , wherein the silicon nitride layer comprises silicon mononitride (SiN).

7. The semiconductor structure of claim 1 , wherein the silicon nitride layer has a thickness of about 45 Angstroms.

8. The semiconductor structure of claim 1 , further comprising a second oxide layer formed on the substrate and along the silicon nitride layer.

9. The semiconductor structure of claim 1 , wherein the first oxide layer comprises a silicon oxide (SiO x ) compound.

10. The semiconductor structure of claim 1 , wherein the first oxide layer comprises a silicon oxide (SiO x ) compound and the silicon nitride layer comprises silicon mononitride (SiN).

11. The semiconductor structure of claim 10 , further comprising a second oxide layer formed on the substrate and along the silicon nitride layer.

12. The semiconductor structure of claim 11 , wherein the second oxide layer comprises an oxidized shallow trench isolation (STI) liner.

13. An integrated circuit comprising:

a substrate;

a silicon-germanium (SiGe) fin disposed on the substrate and comprising a first portion and a second portion, wherein the second portion is disposed on the substrate and the first portion is disposed on the second portion; and

a first oxide layer disposed on the substrate and up to a top surface of the second portion of the SiGe fin and a silicon nitride layer disposed on the substrate and along the first oxide layer,

wherein outer surfaces of sidewalls and a top surface of the first portion of the SiGe fin are Si-rich outer surfaces.

14. The integrated circuit of claim 13 , wherein the Si-rich outer surface is formed from an oxide layer comprising a mixture of a germanium oxide compound and a silicon oxide compound.

15. The integrated circuit of claim 14 , wherein the germanium oxide compound is GeO 2 , and wherein the silicon oxide compound is SiO 2 .

16. The integrated circuit of claim 13 , further comprising a second oxide layer formed on the substrate and along the silicon nitride layer.

17. The integrated circuit of claim 13 , wherein the first oxide layer comprises a silicon oxide (SiO x ) compound.

18. The integrated circuit of claim 13 , wherein the first oxide layer comprises a silicon oxide (SiO x ) compound and the silicon nitride layer comprises silicon mononitride (SiN).

19. The integrated circuit of claim 18 , further comprising a second oxide layer formed on the substrate and along the silicon nitride layer.

20. The integrated circuit of claim 19 , wherein the second oxide layer comprises an oxidized shallow trench isolation (STI) liner.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2017
From: JAGANNATHAN, HEMANTH; LEE, CHOONGHYUN; MOCHIZUKI, SHOGO; WATANABE, KOJI
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 042690/0250 →
Continuity (2)
Division 15215034 · Jul 20, 2016
Related Publication 20180026101A1 · Jan 25, 2018