Vertical transistor using a through silicon via gate
A vertical transistor is described that uses a through silicon via as a gate. In one example, the structure includes a substrate, a via in the substrate, the via being filled with a conductive material and having a dielectric liner, a deep well coupled to the via, a drain area coupled to the deep well having a drain contact, a source area between the drain area and the via having a source contact, and a gate contact over the via.
1. An apparatus comprising: a substrate; a via in the substrate, the via being filled with a conductive material and having a dielectric liner; a deep well coupled to the via, wherein the via extends deeper into the substrate than the deep well; a drain area; coupled to the deep well having a drain contact; a source area between the drain area and the via having a source contact; a gate contact over the via; and an isolation layer above the deep well and between the source area and the drain area, the isolation layer further in direct contact with the deep well and the source area.
2. The apparatus of claim 1 , wherein the via is copper filled.
3. The apparatus of claim 1 , wherein the deep well and the source area are adjacent to the via.
4. The apparatus of claim 1 , further comprising a silicon junction area between the source area and the deep well.
5. The apparatus of claim 4 , wherein the silicon junction area is graded to minimize leakage.
6. The apparatus of claim 1 , wherein the drain area is coupled to the deep well through a well extending from the drain to the deep well.
7. The apparatus of claim 6 , wherein the well is an n-well, the deep well is an n-well, and the substrate is a p-type silicon substrate.
8. The apparatus of claim 1 , wherein the source area surrounds the via and the drain area surrounds the source area.
9. The apparatus of claim 8 , wherein the source area and the drain area are concentric.