Memory device and host device

1. A memory device connectable to a host device, the memory device comprising:

a nonvolatile semiconductor memory; and

a controller which controls the semiconductor memory, wherein the controller includes:

a first memory which stores a first key, the first memory being a nonvolatile memory;

a second memory which stores a second key, the second memory being a volatile memory;

a first generator which generates a third key based on a random number;

a second generator which generates a fourth key based on the first key and the third key; and

an encryptor which encrypts the second key with the fourth key, wherein

the controller transmits the third key and the encrypted second key to the host device in response to first information sent from the host device, the first information indicating that a power supply to the memory device is to be turned off.

2. The memory device according to claim 1 , wherein the transmitted third key and the transmitted encrypted second key are stored in the host device.

3. The memory device according to claim 1 , wherein the controller further includes a decryptor,

the second generator generates the fourth key based on the first key and the third key read from the host device, and

the decryptor decrypts the encrypted second key read from the host device based on the fourth key.

4. The memory device according to claim 3 , wherein, when the power supply to the memory device is turned on, the decryptor decrypts the encrypted second key read from the host device.

5. The memory device according to claim 1 , wherein the third key is stored in the semiconductor memory.

6. The memory device according to claim 5 , wherein, when the power supply to the memory device is turned on, the third key read from the host device is compared with the third key read from the semiconductor memory.

7. The memory device according to claim 1 , wherein the controller further includes a third memory which stores access information on the semiconductor memory, and

the access information is transmitted to the host device before the power supply to the memory device is turned off.

8. The memory device according to claim 7 , wherein the access information is encrypted by the encryptor, and the encrypted access information is stored in the host device.

9. The memory device according to claim 7 , wherein

the controller further includes a third generator which generates a digital signature,

the digital signature is attached to the access information, and

the access information with the digital signature attached thereto is stored in the host device.

10. The memory device according to claim 1 , wherein the third key is a one-time password.

11. The memory device according to claim 1 , wherein, upon receiving the first information from the host device, the controller allows the encryptor to encrypt the second key.

12. The memory device according to claim 1 , wherein,

after transmitting the encrypted second key and the third key, the controller transmits second information indicating that preparation for power supply shutdown is completed, to the host device, and

in response to the second information indicating that preparation for power supply shutdown is completed, the power supply is turned off.

13. A method of controlling a memory device including a nonvolatile semiconductor memory, the method comprising:

storing a first key in a first memory being a nonvolatile memory;

storing a second key in a second memory being a volatile memory;

generating a third key based on a random number;

generating a fourth key based on the first key and the third key;

receiving user data sent from a host device;

encrypting the received user data with the second key;

storing the encrypted received user data in the nonvolatile semiconductor memory;

encrypting the second key with the fourth key;

receiving first information sent from the host device, the first information indicating that a power supply to the memory device is to be turned off; and

transmitting the third key and the encrypted second key to the host device in response to the received first information.

14. The method according to claim 13 , wherein the fourth key is generated based on the first key and the third key read from the host device, and

the method further comprises decrypting the encrypted second key read from the host device based on the fourth key.

15. The method according to claim 14 , wherein the encrypted second key read from the host device is decrypted when the power supply to the memory device is turned on.

16. The method according to claim 13 , further comprising storing the third key in the semiconductor memory.

17. The method according to claim 16 , further comprising comparing the third key read from the host device with the third key read from the semiconductor memory when the power supply to the memory device is turned on.

18. The method according to claim 13 , further comprising:

generating a digital signature,

attaching the digital signature to access information,

encrypting the access information with the digital signature attached thereto, and

transmitting the encrypted access information to the host device before the power supply to the memory device is turned off.

19. The method according to claim 13 , wherein the third key is one-time password.

20. The method according to claim 13 , further comprising:

transmitting second information indicating that preparation for power supply shutdown is completed, to the host device after transmitting the encrypted second key and the third key, by a controller,

wherein the power supply is turned off in response to the second information indicating that preparation for power supply shutdown is completed.