Multiplication and addition device for matrices, neural network computing device, and method

1. A neural network operation device, comprising:

a matrix element memory configured to:

receive a first matrix that includes one or more first values, wherein each of the one or more first values is represented as a sequence that includes one or more bits, and

respectively store the one or more bits in one or more storage spaces in accordance with positions of the one or more bits in the sequence;

a calculator circuit configured to calculate an intermediate result for each storage space based on one or more second values in a second matrix, wherein the one or more second values correspond to non-zero values stored in the storage space; and

an accumulator circuit configured to sum the intermediate results to generate an output value.

2. The neural network operation device of claim 1 , further comprising a submatrix divider circuit configured to select a portion of an input data matrix as the second matrix.

3. The neural network operation device of claim 1 , wherein the one or more bits that represent each of the first values include a sign bit.

4. The neural network operation device of claim 3 , wherein the sign bits of the first values are stored in a sign storage space.

5. The neural network operation device of claim 1 , further comprising a convolution result assembler circuit configured to assemble the output values calculated for different portions of the input data matrix to generate an output matrix.

6. The neural network operation device of claim 1 , wherein the one or more bits are arranged from a least significant bit (LSB) to a most significant bit (MSB) in the sequence.

7. The neural network operation device of claim 1 , wherein the matrix element memory is further configured to:

identify one of the one or more bits of each of the first values at the same position in the sequence, and

store the identified bits at the same position in the sequence in the same storage space.

8. The neural network operation device of claim 1 , wherein the calculator circuit is further configured to:

sum the one or more second values in the second matrix that correspond to the non-zero values in one of the storage spaces to generate a binary intermediate value, and

perform a bitwise shift operation to the binary intermediate value to generate the intermediate result corresponding to one of the storage spaces.

9. The neural network operation device of claim 4 , further comprising a symbol calculator circuit configured to perform an exclusive disjunction operation between signs of the one or more second values and the sign bits stored in the sign storage space to generate a binary result sequence.

10. The neural network operation device of claim 9 , wherein the symbol calculator circuit is further configured to respectively replace the signs of the one or more second values with elements in the binary result sequence.

11. A method for neural network operations, comprising:

receiving, by a matrix element storage module, a first matrix that includes one or more first values, wherein each of the one or more first values is represented as a sequence that includes one or more bits;

respectively storing, by the matrix element storage module, the one or more bits in one or more storage spaces in accordance with positions of the one or more bits in the sequence;

calculating, by a numeric operation module, an intermediate result for each storage space based on one or more second values in a second matrix, wherein the one or more second values correspond to non-zero values stored in the storage space; and

summing, by an accumulation module, the intermediate results to generate an output value.

12. The method of claim 11 , further comprising selecting, by a submatrix dividing module, a portion of an input data matrix as the second matrix.

13. The method of claim 11 , wherein the one or more bits that represent each of the first values include a sign bit.

14. The method of claim 13 , wherein the sign bits of the first values are stored in a sign storage space.

15. The method of claim 11 , further comprising assembling, by a convolution result acquiring module, the output values calculated for different portions of the input data matrix to generate an output matrix.

16. The method of claim 11 , wherein the one or more bits are arranged from a least significant bit (LSB) to a most significant bit (MSB) in the sequence.

17. The method of claim 11 , further comprising:

identifying, by the matrix element storage module, one of the one or more bits of each of the first values at the same position in the sequence; and

storing, by the matrix element storage module, the identified bits at the same position in the sequence in the same storage space.

18. The method of claim 11 , further comprising:

summing, by the numeric operation module, the one or more second values in the second matrix that correspond to the non-zero values in one of the storage spaces to generate a binary intermediate value, and

performing, by the numeric operation module, a bitwise shift operation to the binary intermediate value to generate the intermediate result corresponding to one of the storage spaces.

19. The method of claim 14 , further comprising performing, by a symbolic operation module, an exclusive disjunction operation between signs of the one or more second values and the sign bits stored in the sign storage space to generate a binary result sequence.

20. The method of claim 19 , further comprising respectively replacing, by the symbolic operation module, the signs of the one or more second values with elements in the binary result sequence.