Non-volatile memory semiconductor device and manufacturing method thereof

1. A method of manufacturing a non-volatile memory semiconductor device, comprising:

forming a plurality of memory cells on a non-volatile memory cell area of a semiconductor substrate,

forming a conductive layer over the plurality of memory cells;

forming a first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise over the plurality of memory cells;

performing a planarization operation on the first planarization layer and the conductive layer, thereby removing an upper region of the first planarization layer and an upper region of the conductive layer;

after the planarization operation, forming a hard mask layer on the plurality of memory cells; and

after forming the hard mask layer on the plurality of memory cells, completely removing portions of a lower region of the conductive layer between the memory cells.

2. The method according to claim 1 , wherein each memory cell comprises:

first and second control gates with an erase gate in between the first and second control gates,

first and second select gates located outside the first and second control gates, respectively, and

first and second floating gates formed beneath the first and second control gates, respectively.

3. The method according to claim 1 , further comprising forming a second planarization layer on the memory cells after forming the hard mask layer.

4. The method according to claim 3 , further comprising forming a photoresist layer on the second planarization layer.

5. The method according to claim 1 , wherein a dielectric layer is disposed over the semiconductor substrate, and

wherein a ratio of a thickness T 1 of the conductive layer of the conductive layer measured at a flat surface from an upper surface of the dielectric layer to an uppermost surface of the conductive layer to a thickness T 2 of the conductive layer from an upper surface of the hard mask layer to an uppermost surface of the third conductive layer, T 1 /T 2 , ranges from about 10/1 to about 2/1.

6. The method according to claim 1 , further comprising:

forming a logic area in a peripheral area of the semiconductor substrate spaced apart from the non-volatile memory cell area; and

forming a ground region between the logic area and the cell area.

7. The method according to claim 1 , wherein forming the hard mask layer includes:

forming a first hard mask layer made of a silicon oxide based dielectric material over the plurality of memory cells; and

forming a second hard mask layer made of a silicon nitride based dielectric material over the first hard mask layer.

8. The method according to claim 1 , wherein:

the plurality of memory cells include four memory cells MC 1 , MC 2 , MC 3 , and MC 4 ;

a distance between memory cells MC 1 and MC 2 is equal to the distance between memory cells MC 3 and MC 4 ; and

the distance between memory cells MC 1 and MC 2 is less than a distance between memory cells MC 2 and MC 3 .

9. A method for manufacturing a semiconductor device including a non-volatile memory, the method comprising:

forming, over a substrate, a stacked structure including:

a first polysilicon layer disposed over a first dielectric layer;

a second dielectric layer disposed over the first polysilicon layer;

a second polysilicon layer disposed over the second dielectric layer;

a cap insulating layer disposed over the second polysilicon layer; and

sidewall spacers disposed on opposing sides of the first polysilicon layer, the second dielectric layer, the second polysilicon layer and the cap insulating layer;

forming a third polysilicon layer over the stacked structure, thereby covering the stacked structure;

forming a first planarization layer of a planarization material having a viscosity of less than about 1.2 centipoise over the third polysilicon layer; and

removing the first planarization layer and an upper portion of the third polysilicon layer, thereby forming a select gate and an erase gate.

10. The method according to claim 9 , wherein the first planarization material is an organic material.

11. The method according to claim 9 , wherein a ratio of a thickness T 3 of the first planarization layer as formed measured at a lower flat portion of the third polysilicon layer to a thickness T 4 of the first planarization layer measured at an uppermost flat surface of the third polysilicon layer, T 3 /T 4 , ranges from about 15/1 to about 3/1.

12. The method according to claim 9 , wherein the removing the first planarization layer and the upper portion of the third polysilicon layer comprises:

performing a first etch-back operation using a first plasma process to partially remove the first planarization layer and the third polysilicon layer, thereby exposing the cap insulating layer; and

performing a second etch-back operation using a second plasma process to further reduce a thickness of the third polysilicon layer, thereby forming the select gate and the erase gate.

13. The method according to claim 9 , further comprising forming a hard mask layer on the stacked structure after removing the first planarization layer and an upper portion of the third polysilicon layer.

14. The method according to claim 13 , further comprising forming a second planarization layer on the stacked structure after forming the hard mask layer.

15. The method according to claim 14 , further comprising forming a photoresist layer on the second planarization layer.

16. The method according to claim 15 , further comprising removing the photoresist layer, the second planarization layer, and the hard mask.

17. The method according to claim 14 , wherein the first planarization layer and the second planarization layer are different materials.