Method of fabricating semiconductor device

1. A method of fabricating a semiconductor device, comprising:

providing a hybrid bonded structure;

providing a cover lid comprising a base portion and at least one dummy portion protruding from the base portion;

bonding the at least one dummy portion of the cover lid to the hybrid bonding structure;

removing the base portion; and

forming a redistribution structure over the hybrid bonding structure and the at least one dummy portion.

2. The method as claimed in claim 1 , wherein providing the cover lid comprises:

partially removing portions of a semiconductor substrate to form the base portion and the at least one dummy portion, wherein roughness of side surfaces of the at least one dummy portion ranges between about 0.1 μm and about 0.5 μm.

3. The method as claimed in claim 2 , wherein partially removing portions of the semiconductor substrate comprises performing an etching process.

4. The method as claimed in claim 1 , wherein the cover lid is bonded on the hybrid bonding structure through a wafer-to-wafer bonding tool.

5. A method of fabricating a semiconductor device, comprising:

bonding a plurality of semiconductor dies on a first wafer;

providing a second wafer comprising a base portion and at least one dummy portion protruding from the base portion;

bonding the at least one dummy portion of the second wafer to the first wafer such that the plurality of semiconductor dies are covered by the base portion of the second wafer;

removing the base portion; and

forming a redistribution structure over the first wafer, the plurality of semiconductor dies and the at least one dummy portion.

6. The method as claimed in claim 5 , wherein providing the second wafer comprises:

partially removing portions of a semiconductor substrate to form the base portion and the at least one dummy portion, wherein roughness of side surfaces of the at least one dummy portion ranges between about 0.1 μm and about 0.5 μm.

7. The method as claimed in claim 5 , wherein the semiconductor dies are arranged in a plurality of columns and the at least one dummy portion comprises:

at least one first dummy portion disposed between two adjacent columns among the plurality of columns; and

at least one second dummy portion disposed aside of the at least one first dummy portion, an outermost column among the plurality of columns being between the at least one first dummy portion and the at least one second dummy portion.

8. The method as claimed in claim 7 , wherein the at least one first dummy portion comprises at least one first dummy strip extending along an extending direction substantially parallel to the plurality of columns, and the at least one second dummy portion comprises at least one second dummy strip extending along the extending direction.

9. The method as claimed in claim 8 , wherein dimension of the at least one first dummy strip in the extending direction is substantially equal to or greater than dimension of one column among the plurality of columns in the extending direction.

10. The method as claimed in claim 7 , wherein the at least one dummy portion further comprises:

at least one third dummy portion, disposed between an edge of the first wafer and a die bonding area where the semiconductor dies are distributed.

11. The method as claimed in claim 10 , wherein the at least one third dummy portion is separated from the at least one first dummy portion, and the at least one third dummy portion is separated from the at least one second dummy portion.

12. The method as claimed in claim 10 , wherein the at least one third dummy portion is connected with the at least one first dummy portion, and the at least one third dummy portion is separated from the at least one second dummy portion.

13. The method as claimed in claim 5 , wherein the at least one dummy portion is a dummy frame having a plurality of openings exposing the plurality of semiconductor dies.

14. The method as claimed in claim 5 , wherein the plurality of semiconductor dies are hybrid bonded on the first wafer through a chip-to-wafer bonding tool.

15. The method as claimed in claim 5 , wherein the at least one dummy portion of the second wafer is bonded on the first wafer through a wafer-to-wafer bonding tool.

16. A method of fabricating a semiconductor device, comprising:

bonding a plurality of semiconductor dies on the first wafer;

providing a second wafer comprising a plurality of recesses;

bonding the second wafer to the first wafer such that the plurality of semiconductor dies are accommodated in the plurality of recesses;

removing a portion of the second wafer until the plurality of semiconductor dies are exposed to form at least one dummy portion on the first wafer; and

forming a redistribution structure over the first wafer, the plurality of semiconductor dies and the at least one dummy portion.

17. The method as claimed in claim 16 , wherein providing the second wafer comprise:

partially removing portions of a semiconductor substrate to form the plurality of recesses, wherein roughness of sidewalls of the plurality of recesses ranges between about 0.1 μm and about 0.5 μm.

18. The method as claimed in claim 16 , wherein each one of the plurality of semiconductor dies has at least one through semiconductor via electrically connected to the redistribution structure.

19. The method as claimed in claim 16 , wherein forming the redistribution structure comprises:

forming a dielectric layer, laterally encapsulating the plurality of semiconductor dies and the at least one dummy portion;

forming at least one conductive via, penetrating through the dielectric layer; and

forming a redistribution circuit layer, electrically connected to the plurality of semiconductor dies and the at least one conductive via.

20. The method as claimed in claim 19 , wherein each one of the plurality of semiconductor dies has at least one through semiconductor via electrically connected to the at least one conductive via of the redistribution structure.