Semiconductor device and method of manufacture
A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.
1. A device comprising:
a semiconductor substrate;
an interconnect structure over the semiconductor substrate, the interconnect structure comprising a first conductive feature in a first dielectric layer;
an insulating bonding layer over the first dielectric layer;
a second conductive feature over the first dielectric layer and in the insulating bonding layer;
a first bond pad extending from a top surface of the insulating bonding layer to the first conductive feature; and
a second bond pad extending from a top surface of the insulating bonding layer into the second conductive feature such that the second bond pad is partially embedded in the second conductive feature.
2. The device of claim 1 , wherein the first conductive feature and the second conductive feature have different material compositions.
3. The device of claim 2 , wherein the first conductive feature is a copper interconnect, and wherein the second conductive feature is an aluminum pad.
4. The device of claim 1 , wherein the first conductive feature and the second conductive feature have a same material composition.
5. The device of claim 1 , wherein the first bond pad extends lower than a bottom surface of the second conductive feature.
6. The device of claim 5 further comprising a second dielectric layer between the first dielectric layer and the insulating bonding layer, wherein the first bond pad extends through the second dielectric layer.
7. The device of claim 6 further comprising a conductive via in the second dielectric layer, the conductive via electrically connecting the second conductive feature to a third conductive feature, the third conductive feature being disposed at a same level as the first conductive feature.
8. The device of claim 1 , wherein the second conductive feature is thicker than the first conductive feature.
9. A device comprising:
a device layer comprising a transistor;
a first dielectric layer over the device layer;
a first conductive feature and a second conductive feature in the first dielectric layer, wherein top surfaces of the first dielectric layer, the first conductive feature, and the second conductive feature are level;
an insulating bonding layer over the first dielectric layer;
a third conductive feature over the first dielectric layer and electrically connected to the second conductive feature;
a first bond pad extending through the insulating bonding layer to the first conductive feature; and
a second bond pad extending through the insulating bonding layer to the third conductive feature, wherein the first bond pad extends lower than the second bond pad, and wherein the second bond pad extends below a top surface of the third conductive feature.
10. The device of claim 9 further comprising a third bond pad extending through the insulating bonding layer to the third conductive feature.
11. The device of claim 9 , wherein the first bond pad extends below a bottom surface of the third conductive feature.
12. The device of claim 9 , wherein the third conductive feature is a testing pad configured to provide a pad for circuit testing.
13. The device of claim 9 , wherein the third conductive feature is made of a different metal than the first conductive feature and the second conductive feature.
14. A device comprising:
a device layer comprising a transistor;
a first dielectric layer over the device layer;
a first conductive feature and a second conductive feature in the first dielectric layer, wherein top surfaces of the first dielectric layer, the first conductive feature, and the second conductive feature are level;
a first bonding layer over the first dielectric layer;
a testing pad over the first dielectric layer and electrically connected to the second conductive feature;
a first bond pad extending through the first bonding layer to the first conductive feature, wherein the first bond pad extends lower than a bottom surface of the testing pad; and
a second bond pad through the first bonding layer into the testing pad, wherein the testing pad extends along a sidewall of the second bond pad.
15. The device of claim 14 , further comprising:
a second bonding layer directly bonded to the first bonding layer by oxide-to-oxide bonds;
a third bond pad directly bonded to the first bond pad by metal-to-metal bonds; and
a fourth bond pad directly bonded to the second bond pad by metal-to-metal bonds.
16. The device of claim 14 , wherein the testing pad is an aluminum pad, and wherein the first conductive feature and the second conductive feature are copper interconnects.
17. The device of claim 14 , further comprising a second dielectric layer between the first bonding layer and the first dielectric layer, wherein the first bond pad extends through the second dielectric layer.
18. The device of claim 14 , wherein the second bonding pad comprises:
a bond pad metal at a top surface of the first bonding layer; and
a bond pad via extending from the bond pad metal to the testing pad, the bond pad metal being wider than the bond pad via.
19. The device of claim 14 , wherein the testing pad is disposed in the first bonding layer.
20. The device of claim 14 , wherein the second bond pad comprises:
a seed layer; and
a fill metal over the seed layer, wherein the seed layer extends between the fill metal and the testing pad.