3D integrated circuit and methods of forming the same
An integrated circuit structure includes a package component, which further includes a non-porous dielectric layer having a first porosity, and a porous dielectric layer over and contacting the non-porous dielectric layer, wherein the porous dielectric layer has a second porosity higher than the first porosity. A bond pad penetrates through the non-porous dielectric layer and the porous dielectric layer. A dielectric barrier layer is overlying, and in contact with, the porous dielectric layer. The bond pad is exposed through the dielectric barrier layer. The dielectric barrier layer has a planar top surface. The bond pad has a planar top surface higher than a bottom surface of the dielectric barrier layer.
1. A method of manufacturing a semiconductor device, the method comprising:
pre-bonding a first dielectric barrier layer and a second dielectric barrier layer at room temperature for a time of less than about one minute, wherein the first dielectric barrier layer is adjacent to a first high porosity dielectric layer and the second dielectric barrier layer is adjacent to a second high porosity dielectric layer, wherein the first high porosity dielectric layer is adjacent to a first low porosity dielectric layer and the second high porosity dielectric layer is adjacent to a second low porosity dielectric layer, and wherein a first contact extends through the first low porosity dielectric layer, the first high porosity dielectric layer, and the first dielectric barrier layer to make contact with a second contact, the second contact extending through the second dielectric barrier layer, the second high porosity dielectric layer, and the second low porosity dielectric layer; and
annealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.
2. The method of claim 1 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.
3. The method of claim 1 , wherein when the pre-bonding is performed, the first dielectric barrier layer is a part of an un-sawed first wafer, and the second dielectric barrier layer is a part of an un-sawed second wafer, and wherein the method further comprising, after the pre-bonding, sawing the first wafer and the second wafer.
4. The method of claim 1 , wherein the pre-bonding is performed with a pressing force of less than about 5 Newton per die.
5. The method of claim 1 , further comprising filling an opening with conductive material, the opening extending through the first dielectric barrier layer.
6. The method of claim 1 , wherein the first dielectric barrier layer is a siloxane based polymer.
7. The method of claim 1 , wherein the first dielectric barrier layer has a thickness less than about 1 μm.
8. A method of manufacturing a semiconductor device, the method comprising:
contacting a first contact to a second contact and a first dielectric barrier layer to a second dielectric barrier layer, wherein a first series of layers extend away from the first dielectric barrier layer along the first contact, the first series of layers comprising a first high porosity layer and a first low porosity layer, and wherein a second series of layers extend away from the second dielectric barrier layer along the second contact, the second series of layers comprising a second high porosity layer and a second low porosity layer;
leaving the first dielectric barrier layer and the second dielectric barrier layer at room temperature for a time of less than about one minute; and
annealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.
9. The method of claim 8 , wherein the first low porosity layer is a material with a porosity less than 5 percent.
10. The method of claim 8 , wherein the first dielectric barrier layer comprises a siloxane based polymer.
11. The method of claim 8 , wherein the first contact is a bond pad.
12. The method of claim 8 , further comprising curing the first dielectric barrier layer and the second dielectric barrier layer.
13. The method of claim 8 , wherein when the contacting is performed, the first dielectric barrier layer is a part of an un-sawed first wafer, and the second dielectric barrier layer is a part of an un-sawed second wafer, and wherein the method further comprising, after the contacting, sawing the first wafer and the second wafer.
14. The method of claim 8 , wherein the first dielectric barrier layer has a thickness less than about 1 μm.
15. A method of manufacturing a semiconductor device, the method comprising:
receiving a first semiconductor structure with a first contact, the first contact being surrounded by a first high porosity dielectric layer, a first low porosity dielectric layer, and a first dielectric barrier layer;
receiving a second semiconductor structure with a second contact, the second contact being surrounded by a second high porosity dielectric layer, a second low porosity dielectric layer, and a second dielectric barrier layer;
contacting the first dielectric barrier layer to the second dielectric barrier layer and contacting the first contact to the second contact;
bonding the first dielectric barrier layer and the second dielectric barrier layer at room temperature for a time of less than about one minute; and
annealing the first dielectric barrier layer and the second dielectric barrier layer at a temperature of between about 300° C. and about 400° C.
16. The method of claim 15 , wherein the first dielectric barrier layer is a siloxane based polymer.
17. The method of claim 15 , wherein the first dielectric barrier layer has a thickness less than about 1 μm.
18. The method of claim 15 , wherein when the contacting is performed, the first dielectric barrier layer is a part of an un-sawed first wafer, and the second dielectric barrier layer is a part of an un-sawed second wafer, and wherein the method further comprising, after the contacting, sawing the first wafer and the second wafer.
19. The method of claim 15 , wherein the first low porosity dielectric layer has a porosity of less than 5 percent.
20. The method of claim 15 , wherein the first high porosity dielectric layer has a porosity of greater than 5 percent.