IP Library › Granted Patent US 10,510,770
Granted Patent B2
US 10,510,770 · App. 16/127,763 · Granted Dec 17, 2019

Three-dimensional memory device

Inventors: Hisashi Harada (Yokkaichi, JP); Jun Nishimura (Kuwana, JP); Ayaha Hachisuga (Yokkaichi, JP); Hiroshi Nakaki (Yokkaichi, JP); Yukie Miyazaki (Mie, JP); Keisuke Suda (Yokkaichi, JP); Yu Hirotsu (Kuwana, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11582H01L21/8221H01L23/528H01L23/5226H01L27/0688H01L27/11551H01L27/11565H01L27/11578H01L27/2481H01L29/0649H01L29/1037H01L29/40117H01L21/0217H01L21/0273H01L21/02164H01L21/02532H01L21/02636H01L21/31111H01L21/31144H01L29/513H01L29/518H01L29/66545H01L2224/32145H01L2224/48145
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Quick Facts
Patent No.
US 10,510,770
App. No.
16/127,763
Granted
Dec 17, 2019
Kind
B2
Abstract

A semiconductor device includes a base body portion, a stacked body, a pedestal portion, a plate portion, and first and second columnar portions. The base body portion includes a doped semiconductor film and a semiconductor portion. The doped semiconductor film includes first and second portions. The semiconductor portion includes a first region overlapping the first portion, and a second region overlapping the second portion and being a body different from the first region. The pedestal portion is provided in the second region. The plate portion contacts the pedestal portion and the first region. The first columnar portion includes a semiconductor layer. The semiconductor layer is adjacent to the plate portion with the stacked body interposed, and contacts the first region. The second columnar portion is adjacent to the plate portion with the stacked body interposed, and is adjacent to the pedestal portion with the second region interposed.

Claims (8)

1. A semiconductor device, comprising:

a base body portion including a first layer and a second layer, the first layer being provided on a substrate with at least a first insulating film interposed, the first layer including a first portion and a second portion arranged along a first direction, the first portion being of a semiconductor, the second portion being of a semiconductor, the second layer including a first region and a second region, the first region being positioned on the first portion, the second region being positioned on the second portion, a portion of a source being formed of the first region;

a stacked body provided above the base body portion, the stacked body alternately including a conductive layer and an insulating layer;

a first pedestal portion provided inside at least the second layer, the first pedestal portion including a portion extending in the first direction in the second region of the second layer;

a plate portion including at least a first insulator, being provided from an upper end of the stacked body to the second layer, extending in the first direction, and contacting the first region of the second layer and the portion of the first pedestal portion extending in the first direction;

a plurality of first columnar portions, the plurality of first columnar portions each including a semiconductor layer and a memory film, being provided from the upper end of the stacked body to the second layer, and being adjacent to the plate portion in a second direction with the stacked body interposed, the second direction crossing the first direction, the semiconductor layer contacting the first region of the second layer, the memory film including a charge trapping portion between the semiconductor layer and the conductive layer; and

a plurality of second columnar portions including at least a second insulator, being provided from the upper end of the stacked body to the second layer, being adjacent to the plate portion in the second direction with the stacked body interposed, and being adjacent to the first pedestal portion in the second direction with the second region of the second layer interposed.

2. The device according to claim 1 , wherein the first pedestal portion further includes a portion extending in the second direction between the first region and the second region of the second layer and being connected to the portion extending in the first direction.

Assignments (2)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2019
From: HARADA, HISASHI; NISHIMURA, JUN; HACHISUGA, AYAHA; NAKAKI, HIROSHI; MIYAZAKI, YUKIE; SUDA, KEISUKE; HIROTSU, YU
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 048165/0104 →
Priority Claims (1)
JP 2018-046578 · Mar 14, 2018 · national
Continuity (1)
Related Publication 20190287998A1 · Sep 19, 2019
Cited By (6)
US 12,328,874 US 12,408,344 US 12,538,783 US 12,598,753 US 12,642,075 US 12,713,609