IP Library › Granted Patent US 10,510,840
Granted Patent B2
US 10,510,840 · App. 15/628,243 · Granted Dec 17, 2019

GAA FET with u-shaped channel

Inventors: Jie-Cheng Deng (New Taipei, TW); Yi-Jen Chen (Hsinchu, TW); Chia-Yang Liao (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/1037B82Y10/00H01L29/0673H01L29/1033H01L29/42376H01L29/42392H01L29/495H01L29/4916H01L29/4966H01L29/517H01L29/66439H01L29/66742H01L29/775H01L29/78696
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Quick Facts
Patent No.
US 10,510,840
App. No.
15/628,243
Granted
Dec 17, 2019
Kind
B2
Abstract

A semiconductor device is disclosed. The semiconductor device includes a channel region, extending along a direction, that has a U-shaped cross-section; a gate dielectric layer wrapping around the channel region; and a gate electrode wrapping around respective central portions of the gate dielectric layer and the channel region.

Claims (29)

1. A semiconductor device, comprising:

a channel region, extending along a direction, that has a first U-shaped cross-section, the first U-shaped cross-section having a middle portion, a first extension extending up from a first end of the middle portion, and a second extension extending up from a second end of the middle portion;

a gate dielectric layer completely wrapping around the channel region to form a U-shaped structure having a second U-shaped cross-section that contains the first U-shaped cross-section; and

a gate electrode completely wrapping around the second U-shaped cross-section of the gate dielectric layer, wherein the gate electrode is interposed between the first extension and the second extension.

2. The device of claim 1 , further comprising:

source/drain features disposed at respective side portions of the channel region.

3. The device of claim 1 , wherein the channel region is formed of a semiconductor material selected from: silicon, germanium, silicon-germanium, III-V compound semiconductor materials, and a combination thereof.

4. The device of claim 1 , wherein the gate dielectric layer includes a high-k dielectric material.

5. The device of claim 1 , wherein the first U-shaped cross-section includes a horizontal portion and two vertical portions coupled to respective ends of the horizontal portion.

6. The device of claim 1 , wherein the gate electrode is formed of a material selected from: Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, polysilicon, and a combination thereof.

7. The device of claim 1 , wherein the gate dielectric layer has a thickness that is about 1 to 2 nanometers.

8. A semiconductor device, comprising:

a channel region that comprises a horizontal cross-section and two vertical cross-sections coupled to respective ends of the horizontal cross-section so as to provide a first U-shaped cross-section;

a gate dielectric layer completely wrapping around the channel region to form a U-shaped structure having a second U-shaped cross-section containing the first U-shaped cross-section, wherein the gate dielectric layer is interposed between the two vertical cross-sections of the channel region; and

a gate electrode completely wrapping around the second U-shaped cross-section of the gate dielectric layer between a source region and drain region formed in the channel region.

9. The device of claim 8 , wherein the gate dielectric layer includes a high-k dielectric material.

10. The device of claim 8 , wherein the channel region is formed of a semiconductor material selected from: silicon, germanium, silicon-germanium, III-V compound semiconductor materials, and a combination thereof.

11. The device of claim 8 , wherein the gate electrode is formed of a material selected from: Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, polysilicon, and a combination thereof.

12. A semiconductor device, comprising:

a channel region, extending along a first direction, wherein the channel region has a first U-shaped cross-section including a horizontal portion and two vertical portions coupled to respective ends of the horizontal portion;

a gate dielectric layer completely wrapping around the channel region when viewed as a cross-section of the channel region and the gate dielectric layer, wherein the gate dielectric layer extends between the two vertical portions of the channel region;

a gate electrode completely wrapping around the gate dielectric layer when viewed as the cross-section of the channel region and the gate dielectric layer; and

a source and a drain disposed at respective side portions of the channel region on opposite sides of the gate electrode.

13. The device of claim 12 , wherein the channel region is formed of a semiconductor material selected from: silicon, germanium, silicon-germanium, III-V compound semiconductor materials, and a combination thereof.

14. The device of claim 12 , wherein the gate dielectric layer includes a high-k dielectric material.

15. The device of claim 12 , wherein the gate dielectric layer and the channel region form a U-shaped structure having a second U-shaped cross-section containing the first U-shaped cross-section.

16. The device of claim 12 , wherein the gate electrode is formed of a material selected from: Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, polysilicon, and a combination thereof.

17. The device of claim 12 , wherein the gate dielectric layer has a thickness that is about 1 to 2 nanometers.

18. The device of claim 12 , wherein the gate dielectric layer is formed of a high-k dielectric material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2017
From: DENG, JIE-CHENG; CHEN, YI-JEN; LIAO, CHIA-YANG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 043545/0360 →
Continuity (1)
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