Semiconductor memory device
A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.
1. A semiconductor memory device comprising:
a semiconductor layer;
a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion in a direction along a surface of the semiconductor layer, and a spacer provided between the first portion and the second portion; and
a first insulating layer provided between the semiconductor layer and the gate electrode, the first insulating layer including a first region containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing at least one of a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region,
wherein the first region is positioned between the first portion and the semiconductor layer,
the second region is positioned between the second portion and the semiconductor layer,
the boundary region is positioned between the spacer and the semiconductor layer, and
the boundary region has a chemical composition different from a chemical composition of the spacer.
2. The semiconductor memory device according to claim 1 , wherein
the first portion and the second portion are electrically connected.
3. The semiconductor memory device according to claim 1 , wherein
the boundary region is a paraelectric.
4. The semiconductor memory device according to claim 1 , wherein
a metal element which is a main metal component of the boundary region is identical to a metal element which is a main metal component of the first region and of the second region.
5. The semiconductor memory device according to claim 4 , wherein
the boundary region has a chemical composition identical to a chemical composition of the first region and a chemical composition of the second region.
6. The semiconductor memory device according to claim 1 , further comprising
a second insulating layer provided between the semiconductor layer and the first insulating layer, the second insulating layer having a chemical composition different from a chemical composition of the first insulating layer.
7. The semiconductor memory device according to claim 1 , wherein
the first insulating layer contains hafnium oxide.