Encoding method and memory storage apparatus using the same
An encoding method for a memory storage apparatus adopting a Lien ECC scheme is provided. The memory storage apparatus comprises an ECC encoder using a Lien Code. The encoding method includes: receiving a write command comprising a write address and a write data; reading an existing codeword comprising a first flip bit indicating bit-flipping of the existing codeword and flipping bits of the existing codeword based on the first flip bit; encoding the write data into a new codeword based on a Lien Code by an ECC encoder, and flipping bits of the new codeword based on a number of bits required to be changed from the existing codeword to the new codeword; and writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address In addition, a memory storage apparatus using the encoding method based on the Lien Code is provided.
1. An encoding method for a memory storage apparatus adopting an ECC scheme, comprising:
receiving a write command comprising a write address and a write data;
reading an existing codeword which is a codeword previously stored in the write address, or a codeword with a predefined data pattern;
encoding the write data into a new codeword based on an ECC algorithm by an ECC encoder, wherein one's complement of any codeword of the existing codeword and the new codeword is also a codeword;
flipping bits of the new codeword to minimize a number of bits required to be changed from the existing codeword to the new codeword; and
writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address.
2. The encoding method as claimed in claim 1 , wherein no bit-flipping is performed if the number of bits to be changed is the same as a number of bits not to be changed.
3. The encoding method as claimed in claim 1 , wherein each codeword of the existing codeword and the new codeword comprises the first flip bit contained in a first portion of the codeword and further comprises a second flip bit contained in a second portion of the codeword.
4. The encoding method as claimed in claim 3 , wherein each flip bit of the first flip bit and the second flip bit is determined to minimize the number of bits changed in the first portion or second portion containing the flip bit.
5. The encoding method as claimed in claim 3 , wherein one's complement of the first portion or the second portion of any codeword of the new codeword and the existing codeword is also a codeword.
6. The encoding method as claimed in claim 3 , wherein in each portion of the first portion and the second portion, no bit-flipping is performed if the number of bits to be changed is the same as a number of bits not to be changed.
7. The encoding method as claimed in claim 3 , wherein each flip bit of the first flip bit and the second flip bit is determined to minimize the number of bits changed in parity bits in the first portion or second portion containing the flip bit.
8. The encoding method as claimed in claim 1 , wherein the first flip bit is determined to minimize switching of selected bits in the new codeword and the existing codeword.
9. The encoding method as claimed in claim 8 , wherein the selected bits are parity bits.
10. A memory storage apparatus adopting an ECC scheme, comprising:
a connection interface configured to couple to a host system;
a memory array; and
a memory control circuit coupled to the connection interface and the memory array, and configured to perform an encoding operation in response to receiving a write command comprising a write address and a write data, wherein the encoding operation comprises:
reading an existing codeword which is a codeword previously stored in the write address, or a codeword with a predefined data pattern;
encoding the write data into a new codeword based on an ECC algorithm by an ECC encoder, wherein one's complement of any codeword of the existing codeword and the new codeword is also a codeword;
flipping bits of the new codeword to minimize a number of bits required to be changed from the existing codeword to the new codeword; and
writing the new codeword comprising a first flip bit indicating bit-flipping of the new codeword to the write address.
11. The memory storage apparatus as claimed in claim 10 , wherein the memory control circuit is configured to not perform bit-flipping if the number of bits to be changed is the same as a number of bits not to be changed.
12. The memory storage apparatus as claimed in claim 10 , wherein each codeword of the existing codeword and the new codeword comprises the first flip bit contained in a first portion of the codeword and further comprises a second flip bit contained in a second portion of the codeword.
13. The memory storage apparatus as claimed in claim 12 , wherein the memory control circuit is configured to determine each flip bit of the first flip bit and the second flip bit to minimize the number of bits changed in the first portion or second portion containing the flip bit.
14. The memory storage apparatus as claimed in claim 12 , wherein in each portion of the first portion and the second portion, the memory control circuit is configured to not perform bit-flipping if the number of bits to be changed is the same as a number of bits not to be changed.
15. The memory storage apparatus as claimed in claim 10 , wherein the memory control circuit is configured to determine the first flip bit to minimize switching of selected bits in the new codeword and the existing codeword.