Semiconductor storage device and memory system

Inventors: Weihan Wang (Tokyo, JP); Takahiro Shimizu (Yokohama Kanagawa, JP); Noboru Shibata (Kawasaki Kanagawa, JP)

Assignee: TOSHIBA MEMORY CORPORATION

G11C16/0483 G06F11/1048 G06F11/1068 G06F11/1072 G11C11/5628 G11C11/5642 G11C16/08 G11C16/3459 H03M13/2906

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Quick Facts

Patent No.: US 10,515,700
App. No.: 16/164,622
Granted: Dec 24, 2019
Kind: B2

External Links

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Abstract

A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

Claims (58)

1. A semiconductor storage device comprising:

a first memory string having first, second, and third memory cells and a first select transistor;

a second memory string having fourth, fifth, and sixth memory cells and a second select transistor;

a third memory string having seventh, eighth, and ninth memory cells and a third select transistor;

a first word line that is connected to gates of the first, fourth, and seventh memory cells;

a second word line that is connected to gates of the second, fifth, and eighth memory cells;

a third word line that is connected to gates of the third, sixth, and ninth memory cells;

first, second, and third select gate lines that are respectively connected to the first, second, and third select transistors; and

a row decoder that is connected to the first, second, and third word lines and the first, second, and third select gate lines,

wherein a write operation for writing n-bit data in the memory cells, where n is two or more, includes a first write operation and a second write operation, and

wherein, in the second write operation performed on the memory cells connected to the first word line, the first memory cell is initially selected, in the second write operation performed on the memory cells connected to the second word line, the fifth memory cell is initially selected, and, in the second write operation performed on the memory cells connected to the third word line, the ninth memory cell is initially selected.

2. The semiconductor storage device according to claim 1 , wherein

the second write operation is performed on the memory cells connected to the first word line in an order of the first memory cell, the fourth memory cell, and the seventh memory cell,

the second write operation is performed on the memory cells connected to the second word line in an order of the fifth memory cell, the eighth memory cell, and the second memory cell, and

the second write operation is performed on the memory cells connected to the third word line in an order of the ninth memory cell, the third memory cell, and the sixth memory cell.

3. The semiconductor storage device according to claim 2 , wherein

the first write operation on the second memory cell and the second write operation on the first memory cell are sequentially performed, and

the first write operation on the sixth memory cell and the second write operation on the fifth memory cell are sequentially performed.

4. The semiconductor storage device according to claim 3 , wherein

in the first write operation performed on the memory cells connected to the second word line, the second memory cell is initially selected, and

in the first write operation performed on the memory cells connected to the third word line, the sixth memory cell is initially selected.

5. The semiconductor storage device according to claim 1 , wherein the first write operation is a coarse write operation and the second write operation is a fine write operation.

6. The semiconductor storage device according to claim 1 , wherein the write operation further includes another write operation prior to the first write operation.

7. The semiconductor storage device according to claim 1 , wherein the first, second, and third memory strings are a part of first, second, and third string units, and the second string unit is between the first and third string units.

8. The semiconductor storage device according to claim 1 , wherein the first, second, and third word lines are stacked above a substrate in an order of the first, second, and third word lines.

9. The semiconductor storage device according to claim 1 , wherein the first, second, and third word lines are stacked above a substrate in an order of the third, second, and first word lines.

10. A memory system comprising a semiconductor storage device and a controller, wherein the semiconductor storage device includes: