Selective CVD alignment-mark topography assist for non-volatile memory

1. A method for forming a semiconductor device, the method comprising:

recessing a device pad to below a top surface of an interconnect layer;

depositing a cap in the recess over the device pad;

forming a topography assist layer over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the cap of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap;

depositing device layers conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer; and

aligning the device pad according to the topographical feature.

2. The method as recited in claim 1 , wherein the cap is formed from a metal nitride.

3. The method as recited in claim 2 , wherein the metal nitride includes tantalum nitride.

4. The method as recited in claim 1 , further including forming the device pad in a dielectric layer of the interconnect layer in a device region; and

forming the at least one alignment mark in the dielectric layer of the interconnect layer in an alignment region.

5. The method as recited in claim 4 , further including forming a block mask over the alignment region to recess the device pad.

6. The method as recited in claim 1 , wherein each of the device pad and the at least one alignment mark are formed of copper.

7. The method as recited in claim 1 , wherein the selective deposition process includes chemical vapor deposition of a selective metal.

8. The method as recited in claim 1 , wherein the selective deposition process includes electroless plating of a selective metal.

9. The method as recited in claim 1 , further including forming a memory device in an aligned area over the device pad by removing the device layers outside of the aligned area.

10. The method as recited in claim 1 , further including:

forming vias down to the memory device through a dielectric fill over the interconnect layer and down to the alignment mark through the dielectric fill and the topographic assist layer;

forming vias up to each of the device pad and the alignment k through a substrate and the interconnect layer; and

filling each of the vias with a conductive material to form contacts.

11. A method for forming a semiconductor device, the method comprising:

forming pads in a dielectric layer on a substrate to form an interconnect layer with at least an alignment region and a device region;

patterning a block mask over the alignment region;

recessing a pad in the device region to below a top surface of an interconnect layer;

depositing a metal nitride in the recess over the device pad;

forming a topography assist layer over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad;

depositing device layers conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer; and

aligning the device region according to the topographical feature.

12. The method as recited in claim 11 , wherein each of the device pad and the at least one alignment mark are formed of copper.

13. The method as recited in claim 11 , wherein the selective deposition process includes chemical vapor deposition of a selective metal.

14. The method as recited in claim 11 , wherein the selective deposition process includes electroless plating of a selective metal.

15. The method as recited in claim 11 , further including:

forming vias down to the memory device through a dielectric fill over the interconnect layer and down to the alignment mark through the dielectric fill and the topographic assist layer;

forming vias up to each of the device pad and the alignment mark through the substrate and the interconnect layer; and

filling each of the vias with a conductive material to form contacts.