Semiconductor device and manufacturing method thereof
A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (2D) material. An interfacial layer is formed on the channel structure. A gate stack including a gate electrode layer and a gate dielectric layer is formed over the interfacial layer. Source and drain contacts are formed over openings in the interfacial layer. The source and drain contacts have a side contact with the interfacial layer and a side contact and a surface contact with the channel structure.
1. A semiconductor device, comprising:
a field effect transistor (FET) device including:
a substrate;
a channel structure formed of a two-dimensional (2D) material;
an interfacial layer formed on the channel structure;
a gate stack including a gate electrode layer and a gate dielectric layer formed over the interfacial layer; and
source and drain contacts formed over openings in the interfacial layer, wherein
the interfacial layer continuously covers an entirety of the channel structure, the channel structure extending between the source and drain contacts,
the source and drain contacts contact a side of the interfacial layer, and
the source and drain contacts contact a side and an upper surface of the channel structure.
2. The semiconductor device of claim 1 , wherein the upper surface of the channel structure extends in a first direction perpendicular to the side of the channel structure, and wherein the channel structure comprises a 2D semiconductor comprising a transition metal dichalcogenide (TMD) including molybdenum disulfide (MoS 2 ), black phosphorous, or graphene.
3. The semiconductor device of claim 1 , wherein the interfacial layer comprises a 2D insulator material including at least one of alumina (Al 2 O 3 ) and hexagonal boron nitride.
4. The semiconductor device of claim 1 , wherein the 2D material has a thickness in a range from 1 monolayer to 20 monolayers.
5. The semiconductor device of claim 1 , wherein the gate electrode layer has a gate length smaller than 20 nm.
6. The semiconductor device of claim 1 , wherein the gate electrode layer has a gate width in a range from 30 to 60 nm.
7. The semiconductor device of claim 1 , wherein the gate dielectric layer has a thickness in a range from 0.5 to 10 nm.
8. The semiconductor device of claim 1 , wherein the gate dielectric layer includes a high-k dielectric material.
9. The semiconductor device of claim 8 , wherein the high-k dielectric material comprises metal oxides including oxides of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and mixtures thereof.
10. The semiconductor device of claim 1 , wherein the source and drain contacts are formed of at least one of Al, Cu, W, Ti, Ta, TiN, TiAl, TiAlN, TaN, NiSi, CoSi, and conductive materials with a suitable work function.
11. The semiconductor device of claim 1 , further comprising a metal layer formed over the gate electrodes and the source and drain contacts.
12. The semiconductor device of claim 11 , wherein the metal layer is formed of at least one of aluminum and tungsten.
13. A semiconductor device, comprising:
a field effect transistor (FET) device including:
a substrate;
a channel structure formed of a two-dimensional (2D) material;
isolation structures in the substrate to define a plurality of device regions;
isolated thinned interfacial structures formed on the channel structure;
a gate stack including a gate electrode layer and a gate dielectric layer formed over the isolated thinned interfacial structures; and
source and drain contacts formed over openings in the isolated thinned interfacial structures, wherein
the isolated thinned interfacial structures continuously cover an entirety of the channel structure, the channel structure extending between the source and drain contacts,
the source and drain contacts contact a side of the isolated thinned interfacial structures, and
the source and drain contacts contact a side and a upper surface of the channel structure.
14. The semiconductor device of claim 13 , wherein the upper surface of the channel structure extends in a first direction perpendicular to the side of the channel structure, and wherein the channel structure comprises a 2D semiconductor comprising a transition metal dichalcogenide (TMD) including molybdenum disulfide (MoS 2 ), black phosphorous, or graphene.
15. The semiconductor device of claim 13 , wherein the isolated thinned interfacial structures comprises a 2D insulator material including at least one of alumina (Al 2 O 3 ) and hexagonal boron nitride.
16. The semiconductor device of claim 13 , wherein the 2D material has a thickness in a range from 1 monolayer to 20 monolayers.
17. The semiconductor device of claim 13 , wherein the gate electrode layer has a gate length smaller than 20 nm.
18. The semiconductor device of claim 13 , further comprising a metal layer formed over the gate electrodes and the source and drain contacts.
19. A semiconductor device, comprising:
a field effect transistor (FET) device including:
a substrate;
a channel structure formed of a two-dimensional (2D) material;
isolation structures in the substrate to define a plurality of device regions;
thinned passivation structures formed over the channel structure;
a gate stack including a gate electrode layer and a gate dielectric layer formed over the thinned passivation structures; and
source and drain contacts formed over openings in the thinned passivation structures, wherein
the thinned passivation structures continuously cover an entirety of the channel structure, the channel structure extending between the source and drain contacts,
the source and drain contacts contact a side of the thinned passivation structures, and
the source and drain contacts contact a side and an upper surface of the channel structure.
20. The semiconductor device of claim 19 , further comprising spacers formed over respective thinned passivation structures.