IP Library › Granted Patent US 10,516,410
Granted Patent B2
US 10,516,410 · App. 16/100,534 · Granted Dec 24, 2019

A/D converter and A/D conversion device

Inventors: Shuzo Hiraide (Tokyo, JP); Yasunari Harada (Ebina, JP); Masato Osawa (Tokyo, JP); Hideki Kato (Tokyo, JP)
Assignee: OLYMPUS CORPORATION
H03M1/46H01G4/012H01L23/5223H01L23/5225H01G4/38H01G4/40H03M1/466
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Quick Facts
Patent No.
US 10,516,410
App. No.
16/100,534
Granted
Dec 24, 2019
Kind
B2
Abstract

An A/D converter includes: a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group, in which the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.

Claims (15)

1. An A/D converter comprising:

a first wiring layer including a first A/D conversion circuit including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel, and a second capacitor group in which a plurality of unit capacitors are connected in parallel, the second capacitor group being connected in parallel with the first capacitor group; and

a second wiring layer including a second A/D conversion circuit including a third capacitor group in which a plurality of weighted unit capacitors are connected in parallel, and a fourth capacitor group in which a plurality of unit capacitors are connected in parallel, the fourth capacitor group being connected in parallel with the third capacitor group,

wherein the first wiring layer and the second wiring layer are stacked such that the first A/D conversion circuit and the second A/D conversion circuit are disposed at overlapping positions.

2. The A/D converter according to claim 1 , further comprising: a third wiring layer disposed between the first wiring layer and the second wiring layer and between a set of the first capacitor group and the second capacitor group and a set of the third capacitor group and the fourth capacitor group and connected to a ground electric potential.

3. A successive approximation type A/D converter that includes a sample hold circuit and a comparator, the successive approximation type A/D converter comprising:

a first wiring layer including a first capacitor group in which a plurality of weighted unit capacitors are connected in parallel and which constitutes a DAC capacitor group; and

a second wiring layer including a second capacitor group in which a plurality of unit capacitors are connected in parallel, which is connected to the first capacitor group, and which constitutes an attenuation capacitor group,

wherein the first capacitor group and the second capacitor group are connected in parallel to one end of the sample hold circuit and an input terminal of the comparator, and

the first wiring layer and the second wiring layer are stacked such that the first capacitor group and the second capacitor group are disposed at overlapping positions.

4. The successive approximation type A/D converter according to claim 3 , further comprising: a third wiring layer disposed between the first wiring layer and the second wiring layer, and between the first capacitor group and the second capacitor group and connected to a ground electric potential.

5. The successive approximation type A/D converter according to claim 4 , wherein a ground wiring of the second capacitor group is connected to the third wiring layer.

6. The successive approximation type A/D converter according to claim 3 , wherein bit-input wirings connected to the first capacitor group are formed in the second wiring layer including the second capacitor group.

7. The A/D converter according to claim 1 , wherein each of the first capacitor group and the second capacitor group is a MOM capacitor configured of inter-wiring capacitance generated in a horizontal direction of the same wiring layer.

8. The successive approximation type A/D converter according to claim 3 , wherein each of the first capacitor group and the second capacitor group is a MOM capacitor configured of inter-wiring capacitance generated in a horizontal direction of the same wiring layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2018
From: HIRAIDE, SHUZO; HARADA, YASUNARI; OSAWA, MASATO; KATO, HIDEKI
To: OLYMPUS CORPORATION
Reel/Frame 046612/0939 →
Continuity (2)
Continuation PCTJP2016059925 · Mar 28, 2016
Related Publication 20180351568A1 · Dec 6, 2018
Cited By (1)
US 12,621,933