IP Library › Granted Patent US 10,521,351
Granted Patent B2
US 10,521,351 · App. 15/404,254 · Granted Dec 31, 2019

Temporarily suppressing processing of a restrained storage operand request

Inventors: Bruce C. Giamei (Poughkeepsie, NY); Christian Jacobi (Poughkeepsie, NY); Daniel V. Rosa (Poughkeepsie, NY); Anthony Saporito (Poughkeepsie, NY); Donald W. Schmidt (Poughkeepsie, NY); Chung-Lung K. Shum (Poughkeepsie, NY)
Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
G06F12/0875G06F9/3004G06F9/30047G06F9/30087G06F9/3824G06F12/084G06F12/0811G06F12/0815G06F12/0842G06F12/0862G06F12/1027G06F13/4221G06F2212/452G06F2212/602G06F2212/621G06F2212/68
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Quick Facts
Patent No.
US 10,521,351
App. No.
15/404,254
Granted
Dec 31, 2019
Kind
B2
Abstract

Processing of a storage operand request identified as restrained is selectively, temporarily suppressed. The processing includes determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained, and based on determining that the storage operand request is restrained, then temporarily suppressing requesting access to the common storage location pursuant to the storage operand request. The processing unit performing the processing may proceed with processing of the restrained storage operand request, without performing the suppressing, where the processing can be accomplished using cache private to the processing unit. Otherwise the suppressing may continue until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

Claims (28)

1. A computer program product for facilitating processing within a computing environment, the computer program product comprising:

a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:

determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained;

based on determining that the storage operand request is restrained, temporarily suppressing requesting access to the common storage location pursuant to the storage operand request; and

wherein the suppressing comprises suppressing processing of the storage operand request until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

2. The computer program product of claim 1 , wherein the temporarily suppressing comprises suppressing processing of the storage operand request where the storage operand request requires access to the common storage location shared by the multiple processing units of the computing environment in order to process the storage operand request.

3. The computer program product of claim 2 , wherein the method is performed by a processing unit, and the processing unit further determines whether the storage operand request hits a private cache of the processing unit, and based on the storage operand request producing a hit in the private cache, proceeds with processing of the storage operand request using the private cache, without performing the suppressing.

4. The computer program product of claim 1 , further comprising placing the storage operand request in a queue of storage operand requests where the storage operand request requires access to the common storage location shared by the multiple processing units of the computing environment.

5. The computer program product of claim 1 , further comprising identifying the storage operand request as restrained, the identifying including obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction, the access intent indicating usage of the storage operand request is restrained.

6. The computer program product of claim 5 , wherein the access intent instruction is a next instruction access intent instruction, and the identifying the storage operand request as restrained includes providing a restrain access intent code within the next instruction access intent instruction.

7. The computer program product of claim 1 , wherein the storage operand request is a speculative storage operand request associated with the instruction or the operation of the instruction.

8. A computer system for facilitating processing within a computing environment, the computer system comprising:

a memory; and

a processing unit communicatively coupled with a memory, wherein the computer system configured to perform a method comprising:

determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained;

based on determining that the storage operand request is restrained, temporarily suppressing requesting access to the common storage location pursuant to the storage operand request, and

wherein the suppressing comprises suppressing processing of the storage operand request until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

9. The computer system of claim 8 , wherein the determining and the suppressing are performed within a load storage unit of the processing unit.

10. The computer system of claim 8 , wherein the temporarily suppressing comprises suppressing processing of the storage operand request where the storage operand request requires the access to the common storage location shared by the multiple processing units of the computing environment in order to process the storage operand request.

11. The computer program product of claim 10 , wherein the processing unit further determines whether the storage operand request hits a private cache of the processing unit, and based on the storage operand request producing a hit in the private cache, proceeds with processing of the storage operand request using the private cache, without performing the suppressing.

12. The computer system of claim 8 , wherein the method further includes placing the storage operand request in a queue of storage operand requests where the storage operand request requires access to the common storage location shared by the multiple processing units of the computing environment to complete.

13. The computer system of claim 8 , wherein the method further includes identifying the storage operand request as restrained, the identifying including obtaining, by a processing unit, an access intent instruction indicating an access intent associated with an operand of a next sequential instruction, the access intent indicating usage of the storage operand request is restrained.

14. A computer-implemented method of facilitating processing within a computing environment, the computer-implemented method comprising:

determining whether a storage operand request to a common storage location shared by multiple processing units of a computing environment is restrained;

based on determining that the storage operand request is restrained, temporarily suppressing requesting access to the common storage location pursuant to the storage operand request; and

wherein the suppressing comprises suppressing processing of the storage operand request until an instruction, or operation of an instruction, associated with the storage operand request is next to complete.

15. The computer-implemented method of claim 14 , wherein the temporarily suppressing comprises suppressing processing of the storage operand request where the storage operand request requires access to the common storage location shared by the multiple processing units of the computing environment in order to process the storage operand request.

16. The computer-implemented method of claim 15 , wherein the method is performed by a processing unit, and the processing unit further determines whether the storage operand request hits a private cache of the processing unit, and based on the storage operand request producing a hit in the private cache, proceeds with processing of the storage operand request using the private cache, without performing the suppressing.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2017
From: GIAMEI, BRUCE C.; JACOBI, CHRISTIAN; ROSA, DANIEL V.; SAPORITO, ANTHONY; SCHMIDT, DONALD W.; SHUM, CHUNG-LUNG K.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 040952/0730 →
Continuity (1)
Related Publication 20180196754A1 · Jul 12, 2018