Semiconductor device and system performing calibration operation
A semiconductor device may include a calibration circuit and an output circuit. The calibration circuit may perform a calibration operation for setting a resistance value of the output circuit. The calibrations circuit may perform the calibration operation by being coupled, through a signal transmission line, to a reference resistor provided in another semiconductor device.
1. A semiconductor system comprising:
a controller including a controller calibration circuit configured to receive a first calibration signal, and perform a calibration operation by being coupled to an external reference resistor; and
a memory device including a memory calibration circuit configured to receive a second calibration signal, and perform a calibration operation by being coupled to the external reference resistor,
wherein the memory calibration circuit comprises a first comparator configured to compare a voltage level of a data transmission line with a calibration reference voltage, and
wherein enable periods of the first and second calibration signals do not overlap each other.
2. The semiconductor system according to claim 1 , wherein the controller further includes a controller output circuit coupled to a signal transmission line, and wherein a resistance value of the controller output circuit is set based on a result of the calibration operation of the controller calibration circuit.
3. The semiconductor system according to claim 2 , wherein the memory device further includes a memory output circuit coupled to the signal transmission line, and wherein a resistance value of the memory output circuit is set based on a result of the calibration operation of the memory calibration circuit.
4. The semiconductor system accordingly to claim 1 , wherein the memory calibration circuit further comprises:
a second comparator;
a replica pull-up resistor leg;
and a replica pull-down resistor leg,
wherein the second comparator is configured to compare a voltage level, determined based on a resistance ratio of the replica pull-up resistor leg and the replica pull-down resistor leg, with the calibration reference voltage.
5. The semiconductor system accordingly to claim 1 , wherein the voltage level of the data transmission line is determined based on a resistance ratio of a pull-down resistor leg and a reference resistor leg.
6. The semiconductor system accordingly to claim 1 , wherein the voltage level of the data transmission line is determined based on a resistance ratio of a pull-up resistor leg and a reference resistor leg.