Performing logical operations using sensing circuitry

1. An apparatus, comprising:

an array of memory cells; and

sensing circuitry coupled to the array via a sense line, wherein the sensing circuitry comprises a latch coupled to equilibrate circuitry; and

wherein, responsive to control signals provided thereto, the sensing circuitry is configured to perform one of a first logical function and a second logical function between a first operand stored in a first memory cell and a second operand stored in a second memory cell coupled to the sense line, wherein performing the one of the first and the second logical function comprises:

reading the first memory cell to store a data value corresponding to the first operand in the latch;

if the first logical function is to be performed, subsequently to reading the first memory cell:

responsive to the first memory cell storing a first data value, equilibrating the sense line prior to reading the second memory cell; and

responsive to the first memory cell storing a second data value preventing equilibration of the sense line prior to reading the second memory cell; and

if the second logical function is to be performed, subsequently to reading the first memory cell:

responsive to the first memory cell storing the first data value, preventing equilibration of the sense line prior to reading the second memory cell; and

responsive to the first memory cell storing the second data value, equilibrating the sense line prior to reading the second memory cell.

2. The apparatus of claim 1 , further comprising a controller configured to provide the control signals to the sensing circuitry.

3. The apparatus of claim 1 , wherein the apparatus comprises a memory device, and wherein the array of memory cells comprises dynamic random access memory (DRAM) cells.

4. The apparatus of claim 3 , wherein the apparatus comprises a host coupled to the memory device, the host configured to generate instructions for execution by the memory device.

5. The apparatus of claim 1 , wherein the first logical function is one of an AND logical function and an OR logical function, and wherein the second logical function is the other of the AND logical function and the OR logical function.

6. The apparatus of claim 1 , wherein the sense line is one of a pair of complementary sense lines.

7. The apparatus of claim 6 , wherein the equilibrate circuitry comprises:

a first, a second, and a third transistor having their gates coupled together;

wherein a first source/drain region of the third transistor is coupled to a first source/drain region of the first transistor and to one sense line of the pair of sense lines; and

wherein a second source/drain region of the third transistor is coupled to a first source/drain region of the second transistor and to coupled to the other sense line of the pair of sense lines.

8. The apparatus of claim 6 , wherein the equilibrate circuitry comprises:

a first transistor;

a second transistor; and

a third transistor, wherein:

a first source/drain region of the first transistor is coupled to a first source/drain region of the second transistor and a first one of the pair of complementary sense lines;

a first source/drain region of the third transistor is coupled to a second source/drain region of the second transistor and a second one of the pair of complementary sense lines;

a second source/drain region of the first transistor and a second source/drain region of the second transistor are coupled to a precharge voltage supply; and

a gate of the first transistor is coupled to a gate of the second transistor.

9. The apparatus of claim 8 , wherein the equilibrate circuitry further comprises:

a first source/drain region of a fourth transistor is coupled to an OR logical function control signal line;

a first source/drain region of a fifth transistor is coupled to an AND logical function control signal line;

a second source/drain region of the fourth transistor and a second source/drain region of the fifth transistor are coupled to the gate of the first transistor and the gate of the third transistor;

a gate of the fourth transistor is switchably coupled to the first one of the pair of complementary sense lines; and

a gate of the fifth transistor is switchably coupled to the second one of the pair of complementary sense lines.

10. A system, comprising:

a host configured to generate instructions; and

a memory device coupled to the host and, in association with executing the instructions, configured to perform logical functions on a first digit stored in a first memory cell and a second digit stored in a second memory cell by:

modifying, via a charge corresponding to the first digit stored in the first memory cell, a precharge voltage of a sense line to which the first memory cell is coupled; and

selectively equilibrating the sense line from the modified voltage to the precharge voltage prior to modifying the modified voltage with a charge corresponding to the second digit stored in the second memory cell;

wherein whether the sense line is equilibrated or not prior to modifying the modified voltage with the charge corresponding to the second digit stored in the second memory cell is based on:

a type of a logical function being performed; and

a value of the first digit.

11. The system of claim 10 , wherein the sense line is one of a pair of complementary sense lines.

12. The system of claim 10 , wherein the host comprises one or more processors coupled to the memory device via a bus.

13. The system of claim 10 , wherein the memory device comprises a controller configured to execute at least a portion of the instructions.

14. The system of claim 10 , wherein the precharge voltage is an equilibration voltage.

15. The system of claim 10 , wherein the type of logical function comprises one of an AND logical function and an OR logical function, and wherein the value of the first digit is one of a logic “0” and a logic “1”.

16. A method, comprising:

reading a first data value stored in a first memory cell into a sense amplifier, the first data value serving as a first input of a logical function between the first data value and a second data value stored in a second memory cell and corresponding to a second input of the logical function;

operating equilibrate circuitry to cause voltages corresponding to a result of a selected one of a first logical function and a second logical function between the first data value and the second data value to occur on a pair of complementary sense lines to which the first and second cell are coupled; and

wherein operating the equilibrate circuitry comprises:

if the first logical function is to be performed, subsequently to reading the first memory cell:

responsive to the first memory cell storing a first data value, equilibrating the pair of complementary sense lines prior to reading the second memory cell; and

responsive to the first memory cell storing a second data value, preventing equilibration of the pair of complementary sense lines prior to reading the second memory cell; and

if the second logical function is to be performed, subsequently to reading the first memory cell:

responsive to the first memory cell storing the first data value, preventing equilibration of the pair of complementary sense lines prior to reading the second memory cell; and

responsive to the first memory cell storing the second data value, equilibrating the pair of complementary sense lines prior to reading the second memory cell.

17. The method of claim 16 , wherein the first logical function is one of an AND logical function and an OR logical function, and wherein the second logical function is the other of the AND logical function and the OR logical function.

18. The method of claim 16 , further comprising storing the result of the selected one of the first logical function and the second logical function in the sense amplifier.

19. The method of claim 16 , wherein operating the equilibrate circuitry comprises, subsequently to reading the first memory cell:

enabling a first equilibrate transistor and disabling a second equilibrate transistor responsive to the selected one of the first logical function and the second logical function being the first logical function; and

enabling the second equilibrate transistor and disabling the first equilibrate transistor responsive to the selected one of the first logical function and the second logical function being the second logical function.

20. The method of claim 19 , wherein operating the equilibrate circuitry further comprises enabling a third equilibrate transistor while reading the first memory cell.