High isolation integrated inductor and method thereof
An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.
1. An inductor comprising:
a first coil of metal trace configured in an open loop topology and placed in a first metal layer;
a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and
a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.
2. The inductor of claim 1 , wherein the first coil of metal trace includes an opening located on a side farthest away from the second axis.
3. The inductor of claim 1 , wherein the inductor is housed by a dielectric slab.
4. The inductor of claim 3 , wherein the dielectric slab is placed on a silicon substrate.
5. The inductor of claim 4 , wherein another inductor is also fabricated upon the same silicon substrate.
6. A method comprising:
incorporating a first coil of metal trace, configured in an open loop topology, constructed in a first metal layer, and laid out to be substantially symmetrical with respect to a first axis;
incorporating a second coil of metal trace, configured in an open loop topology, constructed in the first metal layer, and laid out to be approximately a mirror image of the first coil of metal trace with respect with a second axis; and
incorporating a third coil of metal trace, configured in a closed loop topology, constructed in a second metal layer, and laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.
7. The method of claim 6 , wherein the first coil of metal trace includes an opening located on a side farthest away from the second axis.
8. The method of claim 6 , wherein the inductor is housed by a dielectric slab.
9. The method of claim 8 , wherein the dielectric slab is placed on a silicon substrate.
10. The method of claim 9 , wherein another inductor is also fabricated upon the same silicon substrate.