Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.
1. A method for fabricating a semiconductor device, comprising:
preparing a substrate;
forming an isolation layer defining an active region in the substrate;
forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region;
forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions;
forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and
filling the contact hole with a contact plug,
wherein the plug pad includes a central portion formed on the exposed active region, and a side extended portion that grows laterally from the central portion to extend over the isolation layer.
2. The method of claim 1 , wherein a bottom surface of the contact hole is smaller than a surface area of an upper portion of the plug pad.
3. The method of claim 1 , wherein the plug pad includes a silicon-containing epitaxial layer.
4. The method of claim 1 , wherein the plug pad includes a SEG-Si, SEG-SiP, SEG-SiGe, or SEG-SiC.
5. The method of claim 1 , wherein the SEG process is performed by silane (SiH 4 ), dichlorosilane (SiH 2 Cl 2 , DCS), and hydrogen chloride (HCl) at a low temperature ranging from approximately 550° C. to approximately 650° C.
6. The method of claim 1 , wherein the forming of the plug pad includes:
forming a silicon epitaxial layer through the SEG process; and
exposing the silicon epitaxial layer to an annealing process in an ambient of hydrogen.
7. The method of claim 1 , wherein the forming of the first insulation structure includes:
forming a first insulating material over the substrate;
forming a plurality of first insulating layers by etching the first insulating material;
forming a first spacer on both side walls of each of the first insulation layers; and
forming a recess by etching the substrate to be self-aligned to the first spacer.
8. The method of claim 1 , wherein the forming of the second insulation structure:
forming a second spacer over the plug pad and the first insulation structure;
forming a second insulation layer that fills the line-type opening over the second spacer; and
forming the contact hole by etching the second insulation layer and the second spacer to expose the plug pad.
9. The method of claim 1 , wherein the contact plug includes polysilicon, a metal, a metal nitride, or a combination thereof.
10. A method for fabricating a semiconductor device, comprising:
forming an isolation layer that defines a plurality of active regions in a substrate;
forming a plurality of bit lines over the substrate;
forming a line-type opening that is in parallel with the bit lines and exposes at least the active regions between the bit lines;
forming a recess by etching the exposed at least one active region;
performing a Selective Epitaxial Growth (SEG) process to form a plug pad inside the recess, the plug pad contacting the at least one active region;
forming a plug isolation structure defining a contact hole landing on the plug pad; and
filling the contact hole with a contact plug.
11. The method of claim 10 , wherein a cross-section of a bottom surface of the contact hole is formed to be smaller than a cross-section of a surface area of an upper portion of the plug pad.
12. The method of claim 10 , wherein the plug pad includes a central portion formed on the exposed at least one active region, and a side extended portion that laterally grows from the central portion to extend over the isolation layer.
13. The method of claim 10 , wherein the plug pad includes a silicon-containing epitaxial layer.
14. The method of claim 10 , wherein the plug pad includes a SEG-Si, SEG-SiP, SEG-SiGe, or SEG-SiC.
15. The method of claim 10 , wherein the SEG process is performed by using silane (SiH 4 ), dichlorosilane (SiH 2 Cl 2 , DCS), and hydrogen chloride (HCl) at a low temperature ranging from approximately 550° C. to approximately 650° C.
16. The method of claim 10 , wherein the SEG process includes:
forming a silicon epitaxial layer through the SEG process; and
exposing the silicon epitaxial layer to an annealing process in an ambient of hydrogen.
17. The method of claim 10 , wherein the forming of the plug isolation structure includes:
forming a spacer over the plug pad and the line-type opening;
forming a sacrificial layer that fills the line-type opening over the spacer;
forming a plug isolation portion by etching the sacrificial layer;
filling the plug isolation portion with a plug isolation layer;
forming a contact hole by removing the sacrificial layer; and
extending the contact hole by etching the spacer to expose the plug pad.
18. The method of claim 10 , further comprising:
forming a memory element over the contact plug, after the filling the contact hole with a contact plug.
19. The method of claim 10 , wherein the contact plug includes polysilicon, a metal, a metal nitride, or a combination thereof.