Semiconductor device and bump formation process

1. A method of forming a packaging assembly, the method comprising:

forming a solder material layer over a pad region of a first substrate;

reshaping the solder material layer;

forming a metal cap layer along sidewalls of the solder material layer, a first surface of the solder material layer facing the first substrate being free of the metal cap layer, the metal cap layer having a higher melting temperature than the solder material layer, wherein after reshaping the solder material layer, the metal cap layer remains along the sidewalls of the solder material layer; and

bonding the solder material layer to a second substrate.

2. The method of claim 1 , wherein forming the solder material layer comprises:

forming a patterned mask layer over the first substrate, an opening in the patterned mask layer exposing the pad region;

forming a solder material in the opening of the patterned mask layer; and

removing the patterned mask layer.

3. The method of claim 2 , wherein forming the solder material layer further comprises:

forming an under-bump-metallurgy (UBM) layer over the first substrate and over the pad region before forming the patterned mask layer; and

removing portions of the UBM layer uncovered by the solder material layer after removing the patterned mask layer.

4. The method of claim 1 , wherein reshaping the solder material layer comprises performing a thermal reflow process.

5. The method of claim 4 , wherein the solder material layer has straight sidewalls before the reshaping, and wherein the solder material layer has curved sidewalls after the reshaping.

6. The method of claim 1 , wherein forming the metal cap layer is performed before reshaping the solder material layer.

7. The method of claim 1 , wherein reshaping the solder material layer changes a profile of the metal cap layer.

8. The method of claim 1 , wherein the metal cap layer is formed using copper, nickel, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or alloys thereof.

9. The method of claim 1 , wherein the metal cap layer is formed using indium, platinum, cobalt, vanadium, or alloys thereof.

10. The method of claim 1 , wherein the metal cap layer is formed using an electroless process or an immersion metal deposition process.

11. A method of forming a semiconductor package, the method comprising:

forming a solder material layer over a first semiconductor substrate;

forming a metal cap layer conformally over the solder material layer, wherein the metal cap layer is formed over at least sidewalls of the solder material layer while a lower surface of the solder material layer facing the first semiconductor substrate is exposed by the metal cap layer, wherein the metal cap layer has a melting temperature that is greater than a melting temperature of the solder material layer;

reshaping the solder material layer using a heating process, wherein at least the sidewalls of the solder material layer are covered by the metal cap layer after the heating process; and

after reshaping the solder material layer, bonding the solder material layer to a second semiconductor substrate.

12. The method of claim 11 , wherein the solder material layer has straight sidewalls and a flat upper surface prior to the reshaping, wherein the solder material layer has curved sidewalls and a curved upper surface after the reshaping.

13. The method of claim 11 , wherein reshaping the solder material layer comprises performing a reflow process, wherein reshaping the solder material layer also reshapes the metal cap layer.

14. The method of claim 13 , wherein after reshaping the solder material layer, the metal cap layer has rounded corners between an upper surface of the metal cap layer and sidewalls of the metal cap layer.

15. The method of claim 11 , wherein bonding the solder material layer comprises bonding the solder material layer and the metal cap layer to the second semiconductor substrate via a solder region, wherein the metal cap layer is between the solder region and the solder material layer.

16. A method of forming a semiconductor package, the method comprising:

forming a solder pillar on a first substrate, the solder pillar having a first shape;

performing a reflow process to reshape the solder pillar into a second shape different from the first shape;

after performing the reflow process, covering an exterior surface of the solder pillar with a metal cap layer having a multi-layered structure, the metal cap layer having a higher melting temperature than the solder pillar; and

bonding the solder pillar to a second substrate through a solder region, the metal cap layer disposed between the solder region and the solder pillar.

17. The method of claim 16 , wherein the exterior surface of the solder pillar comprises sidewalls of the solder pillar and an upper surface of the solder pillar, wherein a lower surface of the solder pillar bonded to the first substrate is not covered by the metal cap layer.

18. The method of claim 11 , wherein the metal cap layer is further formed over an upper surface of the solder material layer facing away from the first semiconductor substrate.

19. The method of claim 1 , wherein the metal cap layer has a multi-layered structure, wherein each layer of the multi-layered structure comprises a different metal.

20. The method of claim 16 , wherein the solder pillar has straight sidewalls before the reflow process, and wherein the solder pillar has curved sidewalls after the reflow process.