Method for a stacked and bonded semiconductor device

1. A method comprising:

forming a first redistribution layer on a substrate;

plating conductive features on a first side of the first redistribution layer until the conductive features have a first thickness;

covering a first subset of the conductive features with a first photoresist, a second subset of the conductive features not covered by the first photoresist;

plating the second subset of the conductive features until the second subset of the conductive features have a second thickness greater than the first thickness;

removing the first photoresist;

after removing the first photoresist, attaching a die to the first redistribution layer, the die laterally separated from the conductive features;

encapsulating the die and the conductive features with an encapsulant;

after encapsulating the die, removing the substrate;

after removing the substrate, forming a lower passivation layer on a second side of the first redistribution layer;

forming openings through the lower passivation layer to expose portions of the first redistribution layer connected to the conductive features; and

forming solder bumps on exposed portions of the first redistribution layer in the openings, wherein the first redistribution layer is interposed between the conductive features and the solder bumps.

2. The method of claim 1 , wherein the plating the conductive features on the first redistribution layer comprises:

forming an upper passivation layer over the first redistribution layer;

patterning the upper passivation layer with openings exposing the first redistribution layer;

depositing a seed layer over the upper passivation layer and in the openings; and

plating the conductive features from the seed layer.

3. The method of claim 2 , further comprising:

removing portions of the seed layer not covered by the conductive features to expose a portion of the upper passivation layer between each of the conductive features.

4. The method of claim 3 , wherein:

the conductive features have a first width after the plating the conductive features on the first redistribution layer, and

the conductive features have a second width after the removing the portions of the seed layer, the first width greater than the second width.

5. The method of claim 2 , wherein the plating the conductive features from the seed layer comprises:

forming a second photoresist over the seed layer;

patterning the second photoresist to form openings over each of the openings of the upper passivation layer; and

electroplating conductive material from the seed layer in the openings of the upper passivation layer.

6. The method of claim 1 , wherein the plating the second subset of the conductive features comprises:

patterning the first photoresist to form openings over each of the second subset of the conductive features; and

electroplating conductive material from the second subset of the conductive features through the openings of the first photoresist.

7. The method of claim 1 , further comprising:

planarizing the encapsulant such that top surfaces of the encapsulant, the die, and the second subset of the conductive features are level.

8. The method of claim 1 , further comprising:

forming a second redistribution layer over the encapsulant, the die, and the conductive features.

9. The method of claim 1 , further comprising bonding a package to the back side of the first redistribution layer with the solder bumps.

10. The method of claim 1 , wherein:

the conductive features have a first width after the plating the conductive features on the first redistribution layer; and

the openings through the lower passivation layer have a second width, the first width different from the second width.

11. The method of claim 1 , wherein the plating the second subset of the conductive features is performed after the covering the first subset of the conductive features with the first photoresist.

12. A method comprising:

forming a first package comprising:

forming a first redistribution layer on a substrate;

forming a first passivation layer over a front side of the first redistribution layer;

patterning the first passivation layer with openings exposing the first redistribution layer;

forming vias extending from the first redistribution layer and through a first subset of the openings of the first passivation layer;

forming conductive dummy features extending from the first redistribution layer and through a second subset of the openings of the first passivation layer, wherein the conductive dummy features and a portion of the vias are formed in a first plating step, wherein remaining portions of the vias are formed in a second plating step, and wherein the conductive dummy features are covered during the second plating step;

after forming the conductive dummy features, attaching a first die laterally separated from the vias and the conductive dummy features; and

encapsulating the first die, the vias, and the conductive dummy features with an encapsulant; and

attaching a second package to a back side of the first redistribution layer.

13. The method of claim 12 , further comprising using laser drilling to expose portions of the first redistribution layer.

14. The method of claim 13 , wherein the laser drilling comprises a drill energy in a range from 0.1 mJ to about 30 mJ.

15. A method comprising:

forming a first redistribution layer on a substrate;

forming a conductive dummy region on a first portion of the first redistribution layer;

plating a through via on a second portion of the first redistribution layer but not on the first portion of the first redistribution layer, wherein the conductive dummy region and a first through via portion are physically separate and formed in a first plating step, wherein remaining portions of the through via are formed in a second plating step, and wherein the conductive dummy region is covered during the second plating step;

after plating the through via, attaching a first die laterally separated from the through via; and

encapsulating the first die, the conductive dummy region, and the through via with an encapsulant.

16. The method of claim 15 , wherein the forming the conductive dummy region and the through via comprises:

forming a dielectric layer over the first redistribution layer;

patterning the dielectric layer to expose the first portion and the second portion of the first redistribution layer;

depositing a seed layer in contact with the first portion and the second portion of the first redistribution layer; and

wherein the first plating step comprises plating a conductive material to form the conductive dummy region on the seed layer over the first portion and to form the first through via portion over the second portion.

17. The method of claim 16 , wherein the second plating step comprises plating the remaining portions of the through via on the first through via portion.

18. The method of claim 15 , further comprising thinning the encapsulant to expose the through via.

19. The method of claim 18 , further comprising forming a second redistribution layer on a side of the encapsulant opposite the first redistribution layer.

20. The method of claim 15 , further comprising:

forming a passivation layer in contact with the first redistribution layer; and

laser drilling an opening through the passivation layer to expose the first portion of the first redistribution layer.