Memory device
A memory device includes a plurality of gate electrode layers stacked on a substrate, a plurality of channel layers penetrating the plurality of gate electrode layers, a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, and a common source line on the substrate adjacent to the gate electrode layers. The common source line includes a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to a top surface of the substrate. The gate insulating layer includes a plurality of vertical parts and a horizontal part. The plurality of vertical parts surrounds corresponding ones of the plurality of channel layers. The horizontal part extends parallel to a top surface of the substrate.
1. A memory device comprising:
a substrate;
a plurality of gate structures on the substrate, each of the plurality of gate structures including a plurality of gate electrode layers that are stacked on the substrate;
a plurality of channel layers penetrating the plurality of gate electrode layers of respective ones of the plurality of gate structures and extending in a direction perpendicular to a top surface of the substrate;
a horizontal channel layer connecting the plurality of channel layers to the substrate, the horizontal channel layer being below the plurality of gate structures;
a charge storage layer between the plurality of the gate electrode layers and the plurality of channel layers and on a top surface of the horizontal channel layer, the charge storage layer being continuously under at least three stacks of the plurality of gate electrodes; and
a common source line on the substrate between the plurality of gate structures and extending in a first direction that is parallel to a top surface of the substrate,
the substrate including a first impurity region below the horizontal channel layer and a second impurity region between the common source line and the horizontal channel layer.
2. The memory device of claim 1 , further comprising:
a buried insulating layer on the substrate, wherein
the plurality of channel layers surround the buried insulating layer, and
the buried insulating layer extends into the substrate a greater distance compared to the plurality of channel layers.
3. The memory device of claim 1 , wherein the common source line includes a first part and a second part that are alternately arranged in the first direction and have different heights.
4. The memory device of claim 3 , wherein
the substrate includes a plurality of supporting regions protruding toward the first part of the common source line, and
a height of the first part is less than a height of the second part.
5. The memory device of claim 4 , wherein a thickness of the substrate below the first part is greater than a thickness of the substrate below the second part.
6. The memory device of claim 1 , wherein the horizontal channel layer connects at least some of the plurality of channel layers to each other.
7. The memory device of claim 1 , further comprising:
a source region in the substrate and connecting to the common source line, wherein
the source region includes an uneven surface in the first direction.
8. A memory device comprising:
a substrate;
a plurality of gate electrode layers stacked on the substrate;
a plurality of channel layers penetrating the plurality of gate electrode layers;
a gate insulating layer between the plurality of gate electrode layers and the plurality of channel layers, the gate insulating layer including a plurality of vertical parts and a horizontal part, the plurality of vertical parts surrounding respective ones of the plurality of channel layers, the horizontal part being below the plurality of gate electrode layers and extending parallel to a top surface of the substrate;
a common source line on the substrate adjacent to a plurality of gate electrode layers, the common source line including a first part and a second part that are alternately arranged in a first direction and have different heights in a direction vertical to the top surface of the substrate; and
a horizontal channel layer extending parallel to the top surface of the substrate below the plurality of gate electrode layers and connecting at least some of the plurality of channel layers to each other.
9. The memory device of claim 8 , wherein the horizontal part of the gate insulating layer is on a top surface of the horizontal channel layer.
10. The memory device of claim 8 , wherein the substrate includes at least one void below the horizontal channel layer.
11. The memory device of claim 8 , wherein the substrate includes an impurity region adjacent to the horizontal channel layer, and the impurity region includes carbon.
12. A memory device comprising:
a substrate;
a plurality of gate structures on the substrate, each of the plurality of gate structures including a plurality of gate electrode layers that are stacked on the substrate;
a plurality of channel layers penetrating the plurality of gate electrode layers of respective ones of the plurality of gate structures and extending in a direction perpendicular to a top surface of the substrate;
a horizontal channel layer connecting the plurality of channel layers to the substrate, the horizontal channel layer being below the plurality of gate structures;
a charge storage layer between the plurality of the gate electrode layers and the plurality of channel layers and on a top surface of the horizontal channel layer;
a common source line on the substrate between the plurality of gate structures and extending in a first direction that is parallel to a top surface of the substrate,
the substrate including a first impurity region below the horizontal channel layer and a second impurity region between the common source line and the horizontal channel layer, the first and second impurity regions include carbon; and
a source region in the substrate and connecting to the common source line, wherein
the source region includes an uneven surface in the first direction.
13. The memory device of claim 12 , further comprising:
a buried insulating layer on the substrate, wherein
the plurality of channel layers surround the buried insulating layer, and
the buried insulating layer extends into the substrate a greater distance compared to the plurality of channel layers.
14. The memory device of claim 12 , wherein the common source line includes a first part and a second part that are alternately arranged in the first direction and have different heights.
15. The memory device of claim 14 , wherein
the substrate includes a plurality of supporting regions protruding toward the first part of the common source line, and
a height of the first part is less than a height of the second part.
16. The memory device of claim 15 , wherein a thickness of the substrate below the first part is greater than a thickness of the substrate below the second part.
17. The memory device of claim 12 , wherein the horizontal channel layer connects at least some of the plurality of channel layers to each other.