Organic light emitting diode display utilizing a curved semiconductor layer
An organic light emitting diode (OLED) display including: a substrate; a semiconductor layer disposed on the substrate and including a switching semiconductor layer and a driving semiconductor layer connected to the switching semiconductor layer; a first gate insulating layer disposed on the semiconductor layer; a switching gate electrode and a driving gate electrode disposed on the first gate insulating layer and respectively overlapping with the switching semiconductor layer and the driving semiconductor layer; a second gate insulating layer disposed on the switching gate electrode and the driving gate electrode; a driving voltage line configured to transmit a driving voltage and disposed on the second gate insulating layer; an interlayer insulating layer disposed on the driving voltage line and the second gate insulating layer; and a data line configured to transmit a data signal and disposed on the interlayer insulating layer.
1. A display device, comprising:
a substrate;
a plurality of scan lines for transmitting scan signals disposed on the substrate;
a data line for transmitting a data signal and crossing the plurality of scan lines;
a driving voltage line for transmitting a driving voltage;
a first transistor comprising a first semiconductor and a first gate electrode overlapping the first semiconductor, the first transistor including a first source connected to the driving voltage line and receiving the driving voltage through a transistor; and
a second transistor, which includes a second source connected to the data line, and a drain connected to the first source of the first transistor, the second transistor comprising a second semiconductor and a second gate electrode overlapping the second semiconductor,
wherein the driving voltage line comprises a first portion disposed at a layer between the data line and the substrate, and overlapping the data line with a first insulating layer interposed between the data line and the first portion.
2. The display device of claim 1 , wherein the first portion of the driving voltage line overlaps the first semiconductor.
3. The display device of claim 1 , wherein the first portion of the driving voltage line overlaps the first gate electrode with a second insulating layer interposed between the first portion and the first gate electrode.
4. The display device of claim 3 , further comprising a pixel electrode disposed on the first insulating layer.
5. The display device of claim 3 , wherein the first portion of the driving voltage line is disposed at a layer between the data line and the first gate electrode.
6. The display device of claim 1 , wherein the driving voltage line further comprises a second portion which is connected to the first portion and crosses a first scan line of the plurality of scan lines.
7. The display device of claim 1 , wherein the first semiconductor and the second semiconductor are disposed at a same layer and included in a continuous semiconductor layer.
8. The display device of claim 7 , further comprising:
a third transistor comprising a third semiconductor and a third gate electrode overlapping the third semiconductor,
wherein:
the third semiconductor is included in the continuous semiconductor layer, and
a first end of the first semiconductor is connected to the second semiconductor, and a second end of the first semiconductor is connected to the third semiconductor.
9. The display device of claim 8 , wherein a first scan line of the plurality of scan lines overlaps the second semiconductor and the third semiconductor, and comprises the second gate electrode and the third gate electrode.
10. The display device of claim 9 , wherein:
the plurality of scan lines further comprise a second scan line separated from the first scan line; and
the first gate electrode is disposed between the first scan line and the second scan line in a plan view.
11. A display device, comprising:
a semiconductor layer comprising a plurality of channel regions;
a first transistor comprising a first channel region of the plurality of channel regions, a first gate electrode overlapping the first channel region, and a first source region;
a second transistor comprising a second channel region of the plurality of channel regions, and a second gate electrode overlapping the second channel region;
a plurality of scan lines configured to transmit scan signals;
a data line configured to transmit a data signal and crossing the plurality of scan lines;
a driving voltage line configured to transmit a driving voltage and crossing the plurality of scan lines; and
a pixel electrode electrically connected to the first transistor and overlapping a portion of the first gate electrode in a plan view,
wherein:
the semiconductor layer comprises a straight portion that is disposed between the first source region and the second channel region, connected to the first source region and the second channel region, and extends continuously and straight in one direction; and
a portion of the driving voltage line overlaps a portion of the first gate electrode.
12. The display device of claim 11 , wherein a portion of the first channel region is bent in a plan view.
13. The display device of claim 12 , wherein the portion of the driving voltage line overlapping the portion of the first gate electrode forms a capacitor.
14. The display device of claim 13 , wherein the portion of the driving voltage line overlapping the portion of the first gate electrode is disposed at a layer between the data line and the first gate electrode.
15. The display device of claim 11 , wherein a portion of the first channel region has a zig-zag shape.
16. The display device of claim 11 , wherein the straight portion meets the first source region of the semiconductor layer at a substantially right angle.