Semiconductor device

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductive type made of a semiconductor having a bandgap wider than silicon;

a drift region of the first conductive type, made of said semiconductor, over the semiconductor substrate;

one or more first MOS gate structures at or adjacent to a top surface of the drift region, each of the first MOS gate structures including:

a gate electrode,

a gate insulating film,

a source region of the first conductivity type, made of said semiconductor, and

a channel region of a second conductivity type, made of said semiconductor, the channel region being disposed across the gate electrode with the gate insulating film interposed therebetween, and being in contact with the source region on one end and the drift region on another end alongside the gate insulating film, so that when a potential difference between the gate electrode and the channel region exceeds a threshold voltage, an inversion region would be created in the channel region to form a channel between the source region and the drift region;

one or more second MOS gate structures in the top surface of the drift region, each of the second MOS gate structures including:

a gate electrode,

a gate insulating film,

a source region of the first conductivity type, made of said semiconductor, and

a channel region of a second conductivity type, made of said semiconductor, the channel region being disposed across the gate electrode with the gate insulating film interposed therebetween, and being in contact with the source region on one end and the drift region on another end alongside the gate insulating film, so that when a potential difference between the gate electrode and the channel region exceeds a threshold voltage, an inversion region would be created in the channel region to form a channel between the source region and the drift region;

a source electrode over the first and second MOS gate structures, the source electrode being electrically connected to the source region of each of the first and second MOS gate structures; and

a drain electrode under the semiconductor substrate,

wherein the first MOS gate structures and the second MOS gate structures are arranged side-by-side in a plan view and when the first and second MOS gate structures are both provided in a plurality, a group consisting of a prescribed number of the first MOS gate structures and a prescribed number of the second MOS gate structures that are arranged in a prescribed arrangement is repeatedly arranged in the plan view, and

wherein at least one of physical properties of the respective gate electrodes, the respective gate insulating films, and the respective channel regions of the first and second MOS structures is made different between the first MOS structure and the second MOS structure such that the threshold voltage of each of the first MOS gate structures is greater than the threshold voltage of each of the second MOS gate structures.

2. The semiconductor device according to claim 1 , wherein a thickness of the gate insulating film of the second MOS gate structure is less than a thickness of the gate insulating film of the first MOS gate structure.

3. The semiconductor device according to claim 1 , wherein at least a portion of the gate insulating film of the second MOS structure has a higher dielectric constant than the gate insulating film of the first MOS gate structure.

4. The semiconductor device according to claim 1 ,

wherein the first conductivity type is n-type,

wherein the second conductivity type is p-type, and

wherein a material of the gate electrode of the second MOS gate structure has a higher Fermi level than a material of the gate electrode of the first MOS gate structure.

5. The semiconductor device according to claim 4 ,

wherein the material of the gate electrode of the first MOS gate structure is p-type polysilicon, and

wherein the material of the gate electrode of the second MOS gate structure is n-type polysilicon.

6. The semiconductor device according to claim 1 ,

wherein the first conductivity type is p-type,

wherein the second conductivity type is n-type, and

wherein the material of the gate electrode of the second MOS gate structure has a lower Fermi level than the material of the gate electrode of the first MOS gate structure.

7. The semiconductor device according to claim 6 ,

wherein the material of the gate electrode of the first MOS gate structure is n-type polysilicon, and

wherein the material of the gate electrode of the second MOS gate structure is p-type polysilicon.

8. The semiconductor device according to any one of claim 1 ,

wherein each of the first and second MOS gate structures further includes a JFET region that is a portion of the drift region,

wherein each of the first and second MOS gate structures is a planar gate structure in which the source region, the channel region, and said JFET region of the drift region are arranged laterally, and the gate electrode is disposed laterally via the gate insulating film over the source region, the channel region and said JFET region of the drift region, and

wherein a width of said JFET region of the second MOS gate structure is narrower than a width of said JFET region of the first MOS gate structure.

9. The semiconductor device according to claim 1 ,

wherein each of the first and second MOS gate structures is a trench gate structure in which the gate insulating film and the gate electrode are disposed in a trench that extends vertically from a top towards a bottom, and the source region, the channel region, and said JFET region of the drift region are arranged vertically alongside the trench,

wherein each of the first and second MOS gate structures further includes:

a first semiconductor region of the second conductivity type that is selectively disposed inside the drift region so as to be separated from the channel region and surround a bottom surface of the trench;

a second semiconductor region of the second conductivity type, selectively disposed inside the drift region, between the adjacent trenches, and contacting the channel region; and

a JFET region that is a portion of the drift region interposed between the first semiconductor region and the second semiconductor region, and

wherein a width of said JFET region of the second MOS gate structure is narrower than a width of said JFET region of the first MOS gate structure.

10. The semiconductor device according to claim 1 , wherein the gate electrode of each of the second MOS gate structures is connected to the source electrode of the second MOS gate structure to have a potential fixed to a potential of the source electrode.

11. The semiconductor device according to claim 1 ,

wherein each of the first and second MOS gate structures further includes a contact region of the second conductivity type that is selectively disposed in the channel region so as to contact the source region and has a higher impurity concentration than the channel region, and

wherein the contact region is in contact with the source electrode, and a contact area between the source electrode and the contact region is less than or equal to 1/10 of a contact area between the source electrode and the source region.

12. The semiconductor device according to claim 11 ,

wherein each of the first and second MOS gate structures further includes another electrode that forms a Schottky junction with the channel region, and

wherein the source electrode forms an ohmic junction with the contact region.

13. The semiconductor device according to claim 1 ,

wherein a plurality of the first and second MOS gate structures are arranged in parallel in a growth direction of belt shape stacking faults in said semiconductor.