Semiconductor memory with a multi-layer passivation layer formed over sidewalls of a variable resistance element

1. An electronic device comprising a semiconductor memory device which includes:

a variable resistance element formed over a substrate and comprising a stacked layer of two magnetic layers and a tunnel barrier layer interposed therebetween;

a multi-layer passivation layer formed over sidewalls of the variable resistance element and including two or more insulating layers perpendicular to the stacked layer of two magnetic layers and a tunnel barrier layer; and

a reduction region having a reduction degree to reduce an amount of an oxidation material on the sidewalls of the variable resistance element and formed between the multi-layer passivation layer and one of the sidewalls of the variable resistance element to contact the sidewalls of the variable resistance element, the reduction region covering sidewalls of the two magnetic layers and the sidewalls of the tunnel barrier layer and the reduction degree determined based on the number of insulating layers included in the multi-layer passivation layer,

wherein among the two or more insulating layers of the multi-layer passivation layer, a first insulating layer has a first impurity concentration higher than a second impurity concentration of a second insulating layer positioned closer than the first insulating layer to the variable resistance element.

2. The electronic device according to claim 1 , wherein the insulating layer comprises silicon nitride.

3. The electronic device according to claim 1 , wherein each insulating layer includes a thin film formed through a deposition and a post-treatment.

4. The electronic device according to claim 1 , wherein the variable resistance element comprises a stacked layer of two magnetic layers and a tunnel barrier layer interposed therebetween.

5. The electronic device according to claim 1 , wherein the variable resistance element comprises a metal oxide.

6. The electronic device according to claim 1 , wherein the variable resistance element comprises a phase change material.

7. The electronic device according to claim 1 , wherein:

the variable resistance element includes different layers that are formed over the substrate and are parallel to the substrate, and

the two or more insulating layers are perpendicular to the different layers of the variable resistance element.

8. The electronic device according to claim 7 , wherein the two or more insulating layers have a total thickness smaller than a total thickness of the different layers of the variable resistance element.

9. The electronic device according to claim 1 , further comprising a microprocessor which includes:

a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of the signal of the microprocessor;

an operation unit configured to perform an operation based on a result that the control unit decodes the command; and

a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address corresponding to data for which the operation is performed,

wherein the semiconductor memory device that includes the variable resistance element is a part of the memory unit in the microprocessor.

10. The electronic device according to claim 1 , further comprising a processing system which includes:

a processor configured to decode a command received by the processor and control an operation based on a result of decoding the command;

an auxiliary memory device configured to store a program for decoding the command and the information;

a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and

an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside,

wherein the semiconductor memory device that includes the variable resistance element is a part of the auxiliary memory device or the main memory device in the processing system.

11. The electronic device according to claim 1 , further comprising a data storage system which includes:

a storage device configured to store data and conserve stored data regardless of power supply;

a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside;

a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and

an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside,

wherein the semiconductor memory device that includes the variable resistance element is a part of the storage device or the temporary storage device in the data storage system.

12. The electronic device according to claim 1 , further comprising a memory system which includes:

a memory configured to store data and conserve stored data regardless of power supply;

a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside;

a buffer memory configured to buffer data exchanged between the memory and the outside; and

an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside,

wherein the semiconductor memory device that includes the variable resistance element is a part of the memory or the buffer memory in the memory system.

13. The electronic device according to claim 1 , wherein the two magnetic layers have sidewalls that are aligned to each other.

14. The electronic device according to claim 1 , wherein the reduction region has a height as same as that of the multi-layer passivation layer.