Disabling cache portions during low voltage operations
Methods and apparatus relating to disabling one or more cache portions during low voltage operations are described. In some embodiments, one or more extra bits may be used for a portion of a cache that indicate whether the portion of the cache is capable at operating at or below Vccmin levels. Other embodiments are also described and claimed.
1. A method comprising:
receiving a request to access a cache line set of a plurality of cache line sets in a first power mode wherein the first power mode uses a low voltage level to access cache lines at or lower than a minimum voltage level at which all memory cells of the cache may operate reliably;
determining a cache line of a first way of the cache line set is operable in the first power mode based at least in part on one or more disable bits corresponding to the cache line of the first way;
returning a hit at least in part responsive to the cache line of the first way of the cache line set being determined operable in the first power mode.
2. The method of claim 1 , further comprising:
receiving a request to enter the first power mode; and
not flushing the cache line of the first way of the cache line set responsive to the first way of the cache line set being determined operable in the first power mode.
3. The method of claim 2 , further comprising testing a portion of the cache to determine whether the portion of the cache is operable at the low voltage level, wherein the testing is to be performed during manufacturing.
4. The method of claim 3 further comprising updating the one or more bits in response to the testing.
5. An apparatus comprising:
a cache;
replacement logic circuitry to detect access to a portion of the cache and determine whether the portion of the cache is operable at first voltage level based on one or more bits corresponding to the portion of the cache, wherein the first voltage level is at or lower than a minimum voltage level and the minimum voltage level corresponds to a voltage level at which all memory cells of the cache may operate reliably.
6. The apparatus of claim 5 , wherein the portion of the cache comprises one or more of cache lines or subblocks of cache lines.
7. The apparatus of claim 5 , wherein the replacement logic circuitry is to test the portion of the cache to determine whether the portion of the cache is operable at the first voltage level.
8. The apparatus of claim 7 , wherein the replacement logic circuitry is to update the one or more bits in response to test results generated.
9. The apparatus of claim 5 , wherein the one or more bits comprise one or more redundant bits.
10. The apparatus of claim 5 , wherein the access to the portion of the cache results in a miss in response to the one or more bits even if there is a hit in a corresponding tag.
11. The apparatus of claim 5 , wherein a given address of the portion of the cache maps to different cache sets at different times.
12. The apparatus of claim 5 , further comprising a counter used in calculating a given address, resulting in the given address being mapped to different cache sets at different times.
13. The apparatus of claim 5 , wherein the cache comprises a level 1 cache, a mid-level cache, or a last level cache.