SRAM cell having SiGe PMOS fin lines

1. A Static Random Access Memory (SRAM) cell comprising:

a P-type well (P-well) region;

a first N-type well (N-well) region and a second N-well region on opposite sides of the P-well region;

a plurality of Si fins in the P-well region;

at least one SiGe fin in the first N-well region;

at least one SiGe fin in the second N-well region;

a first pass-gate field effect transistor (FET) and a first pull-up FET formed over the at least one SiGe fin in the first N-well region;

a second pass-gate FET and a second pull-up FET formed over the at least one SiGe fin in the second N-well region;

a first pull-down FET formed over one of the plurality of Si fins in the P-well region; and

a second pull-down FET formed over another of the plurality of Si fins in the P-well region,

wherein channel regions of the first and second pass-gate FETs and the first and second pull-up FETs include first SiGe alloy, and source/drain regions of the first and second pass-gate FETs and the first and second pull-up FETs include second SiGe alloy, wherein the first SiGe alloy is different from the second SiGe alloy in composition or impurity doping.

2. The SRAM cell of claim 1 , wherein the source/drain regions of the first and second pass-gate FETs and the first and second pull-up FETs include a P-type dopant and the channel regions of the first and second pass-gate FETs and the first and second pull-up FETs are substantially free of the P-type dopant.

3. The SRAM cell of claim 1 ,

wherein the source/drain regions of the first and second pass-gate FETs and the first and second pull-up FETs include epitaxial features,

wherein the channel regions of the first and second pass-gate FETs and the first and second pull-up FETs comprise a first Ge concentration,

wherein the epitaxial features comprise a second Ge concentration greater than the first Ge concentration.

4. The SRAM cell of claim 3 , wherein the first Ge concentration is between about 10% and about 40%.

5. The SRAM cell of claim 3 , wherein the second Ge concentration is between about 30% and about 75%.

6. The SRAM cell of claim 1 , further comprising:

a first metal layer comprising a bit-line (BL) and a bit-line bar (BLB) of the SRAM cell;

a second metal layer over the first metal layer, the second metal layer comprising a word line (WL) coupled to gates of the first and second pass-gate FETs; and

a third metal layer over the second metal layer, the third metal layer comprising power supply (Vdd) conductors electrically coupled to source regions of the first and second pull-up FETs,

wherein the second metal layer comprises a thickness greater than a thickness of the first metal layer and a thickness of the third metal layer.

7. The SRAM cell of claim 1 ,

wherein the SRAM cell comprises a first boundary and a second boundary parallel to the first boundary,

wherein the at least one SiGe fin in the first N-well region is continuous between the first boundary and the second boundary,

wherein the at least one SiGe fin in the second N-well region is continuous between the first boundary and the second boundary.

8. A Static Random Access Memory (SRAM) cell comprising:

a first P-type pull-up field effect transistor (FET) and a first N-type pull-down FET, the first P-type pull-up FET and the first N-type pull-down FET forming a first inverter;

a second P-type pull-up FET and a second N-type pull-down FET, the second P-type pull-up FET and the second N-type pull-down FET forming a second inverter;

a first P-type pass-gate FET coupled to an output of the first inverter and an input of the second inverter; and

a second P-type pass-gate FET coupled to an output of the second inverter and an input of the first inverter,

wherein each of the first and second P-type pass-gate FETs and the first and second P-type pull-up FETs comprise a fin having a SiGe channel region and two SiGe source/drain regions sandwiching the SiGe channel region,

wherein the SiGe channel region comprises a first Ge concentration and the SiGe source/drain region comprises a second Ge concentration greater than the first Ge concentration.

9. The SRAM cell of claim 8 , wherein the first Ge concentration is between about 15% and about 35%.

10. The SRAM cell of claim 8 , wherein the second Ge concentration is between about 35% to about 70%.

11. The SRAM cell of claim 8 , wherein the SiGe source/drain region comprises a P-type dopant and the SiGe channel region is substantially free of the P-type dopant.

12. The SRAM cell of claim 11 , wherein the P-type dopant is boron.

13. The SRAM cell of claim 8 , wherein each of the first and second N-type pull-down FETs comprise another fin having a Si channel region and two Si source/drain regions sandwiching the Si channel region.

14. The SRAM cell of claim 8 , further comprising:

a first metal layer comprising a bit-line (BL) and a bit-line bar (BLB) of the SRAM cell;

a second metal layer over the first metal layer, the second metal layer comprising a word line (WL) coupled to gates of the first and second P-type pass-gate FETs; and

a third metal layer over the second metal layer, the third metal layer comprising power supply (Vdd) conductors electrically coupled to source regions of the first and second P-type pull-up FETs,

wherein the second metal layer comprises a thickness greater than a thickness of the first metal layer and a thickness of the third metal layer.

15. A Static Random Access Memory (SRAM) cell comprising:

a first P-type pass-gate field effect transistor (FET) including a gate;

a second P-type pass-gate FET including a gate;

a first P-type pull-up FET including a source region;

a second P-type pull-up FET including a source region;

a first N-type pull-down FET;

a second N-type pull-down FET;

a first metal layer comprising a bit-line (BL) and a bit-line bar (BLB) of the SRAM cell;

a second metal layer over the first metal layer, the second metal layer comprising a word line (WL) coupled to the gates of the first and second P-type pass-gate FETs; and

a third metal layer over the second metal layer, the third metal layer comprising power supply (Vdd) conductors electrically coupled to the source regions of the first and second P-type pull-up FETs,

wherein the second metal layer comprises a thickness greater than a thickness of the first metal layer and a thickness of the third metal layer as measured along a direction perpendicular to a top surface of the first metal layer.

16. The SRAM cell of claim 15 ,

wherein the first P-type pass-gate FET and the first P-type pull-up FET are formed over at least one SiGe fin in a first N-type well (N-well) region of the SRAM cell,

wherein the second P-type pass-gate FET and the second P-type pull-up FET are formed over at least one SiGe fin in a second N-well region of the SRAM cell,

wherein the first and second N-type pull-down FETs are each formed over a Si fin in a P-type well (P-well) region of the SRAM cell,

wherein the P-well region is disposed between the first N-well region and the second N-well region.

17. The SRAM cell of claim 15 ,

wherein source/drain regions of the first and second P-type pass-gate FETs and the first and second P-type pull-up FETs include epitaxial features,

wherein channel regions of the first and second P-type pass-gate FETs and the first and second P-type pull-up FETs comprise a first Ge concentration,

wherein the epitaxial features comprise a second Ge concentration greater than the first Ge concentration.

18. The SRAM cell of claim 17 ,

wherein the first Ge concentration is between about 10% and about 40%,

wherein the second Ge concentration is between about 30% to about 75%.

19. The SRAM cell of claim 15 , wherein source/drain regions of the first and second P-type pass-gate FETs and the first and second P-type pull-up FETs include a P-type dopant and channel regions of the first and second P-type pass-gate FETs and the first and second P-type pull-up FETs are substantially free of the P-type dopant.

20. The SRAM cell of claim 19 , wherein the P-type dopant is boron.