Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device
Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
1. A semiconductor device, comprising:
a FET (field effect transistor) device formed on a semiconductor substrate, wherein the FET device comprises:
a silicon-germanium (SiGe) channel layer comprising a chemically treated surface; and
a metal gate structure formed on the SiGe channel layer, wherein the metal gate structure comprises:
an interfacial silicon dioxide layer grown on the chemically treated surface of the SiGe channel layer, wherein the chemically treated surface of the SiGe layer is configured to prevent formation of germanium oxide and prevent incorporation of nitrogen within the interfacial silicon dioxide layer such that the interfacial silicon dioxide layer is substantially devoid of germanium oxide and nitrogen;
a high-k dielectric layer formed on the interfacial silicon dioxide layer, wherein k is greater than 4; and
a metal gate electrode layer formed over the high-k dielectric layer.
2. The semiconductor device of claim 1 , wherein the interfacial silicon dioxide layer is grown on the surface of the SiGe channel layer using an oxynitridation process which comprises performing a first rapid thermal anneal process in a gas mixture atmosphere comprising ammonia (NH 3 ) at a first temperature, and performing a second rapid thermal anneal process in a gas mixture atmosphere comprising oxygen (O 2 ) at a second temperature.
3. The semiconductor device of claim 1 , wherein the SiGe channel layer comprises a Ge content in a range of about 20% to about 70%.
4. The semiconductor device of claim 1 , wherein the metal gate structure further comprises a conformal work function metal layer formed on the high-k dielectric layer.
5. The semiconductor device of claim 1 , wherein the FET device comprises a planar FET device.
6. The semiconductor device of claim 1 , wherein the FET device comprises a three-dimensional FET device.
7. The semiconductor device of claim 6 , wherein the three-dimensional FET device comprises a FinFET device.
8. The semiconductor device of claim 1 , wherein the chemically treated surface of the SiGe channel layer is formed by a process which comprises:
growing a silicon oxide layer on the surface of the SiGe channel layer using a first oxynitridation process, wherein the silicon oxide layer comprises nitrogen, and wherein the growth of the silicon oxide layer using the first oxynitridation process serves to chemically treat the surface of the SiGe channel layer, and
removing the silicon oxide layer to expose the chemically treated surface of the SiGe channel layer.
9. The semiconductor device of claim 8 , wherein the interfacial silicon dioxide layer is grown on the chemically treated surface of the SiGe channel layer using an oxynitridation process which is the same or similar to the first oxynitridation process.