Pulse-frequency control circuit, microcomputer, DC-to-DC converter, and pulse-frequency control method
View Patent ↗A pulse-frequency control circuit includes: a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period; a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks, in which the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.
1. A pulse-frequency control circuit, comprising:
a selection circuit that receives, and selects from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period;
a setting register that stores information for identifying a setting period that is in increments of a first duration shorter than the reference period; and
a control circuit that causes, based on the information stored in the setting register, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks,
wherein the selection circuit sequentially and repeatedly generates an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.
2. The pulse-frequency control circuit according to claim 1 , wherein
the control circuit sequentially and repeatedly generates a normal pulse having a period that is M times the reference period, to generate a normal pulse sequence of the normal pulses, M being an integer greater than or equal to 1, and
a value of M is changed to I under a predetermined condition, I being an integer greater than or equal to 1.
3. The pulse-frequency control circuit according to claim 1 , wherein
the plurality of reference clocks comprise N reference clocks whose phases differ by 1/N of the reference period from one another, N being an integer greater than or equal to 2,
the first duration is 1/N of the reference period,
M is an integer part of a quotient obtained by dividing the setting period by the reference period,
the setting register comprises a first register that stores first information for identifying M, and a second register that stores second information for identifying a fractional part L of the quotient, L being a decimal fraction greater than or equal to 0 and less than 1,
the control circuit sequentially and repeatedly generates, based on the first information stored in the first register, a normal pulse having a period that is M times the reference period, to generate a normal pulse sequence of the normal pulses,
the pulse-frequency control circuit further includes a cumulative adder circuit that: cumulatively adds L/2 based on the second information stored in the second register every time a rising edge or a falling edge occurs in the output pulse sequence provided from the selection circuit; and calculates cumulative sum LL(J) when L/2 is added J times, where J is an integer greater than or equal to 0, and
the control circuit causes, based on the second information stored in the second register, the selection circuit to perform the selection by selecting, as the determined rising edge in K-th selection, a rising edge of one of the plurality of reference clocks which is delayed relative to a first rising edge of the normal pulse sequence by a duration that is LL(2×K) times the reference period, and as the determined rising edge in (K+1)-th selection, a rising edge of one of the plurality of reference clocks which is delayed relative to a rising edge following the first rising edge of the normal pulse sequence by a duration that is LL(2×(K+1)) times the reference period, K being an integer greater than or equal to 0.
4. The pulse-frequency control circuit according to claim 3 , wherein
when LL(J) obtained by cumulatively adding L/2 is greater than or equal to 1, the cumulative adder circuit (i) calculates new LL(J) by subtracting 1 from the LL(J) obtained, (ii) updates the first information stored in the first register from information for identifying M to information for identifying M+1, and (iii) further updates the first information stored in the first register from the information for identifying M+1 to the information for identifying M at a time when a rising edge occurs first after the update (ii) in the output pulse sequence provided from the selection circuit.
5. The pulse-frequency control circuit according to claim 4 , wherein
M is an integer greater than or equal to 2,
the setting register further comprises a third register that stores third information for identifying an integer P, P being an integer greater than or equal to 1 and less than M,
when causing the selection circuit to select, as a first determined rising edge, the rising edge of one of the plurality of reference clocks which is delayed relative to the first rising edge of the normal pulse sequence by the duration that is LL(2×K) times the reference period, the control circuit further causes, based on the third information stored in the third resister, the selection circuit to select, as a first determined falling edge corresponding to the first determined rising edge, a rising edge of one of the plurality of reference clocks which is delayed relative to the first rising edge by a duration that is P+LL(2×K+1) times the reference period, and
the selection circuit generates the output pulse whose rising edge coincides with the first determined rising edge and whose falling edge coincides with the first determined falling edge.
6. The pulse-frequency control circuit according to claim 5 , wherein
when LL(J) obtained by cumulatively adding L/2 is greater than or equal to 1, the cumulative adder circuit (i) updates the third information stored in the third resister from information for identifying P to information for identifying P+1, and (ii) further updates the third information stored in the third register from the information for identifying P+1 to the information for identifying P at a time when a rising edge occurs first after the update (i) in the output pulse sequence provided from the selection circuit.
7. The pulse-frequency control circuit according to claim 1 , further comprising:
a reference clock generation circuit that generates the plurality of reference clocks from an input reference clock having the reference period, the plurality of reference clocks being received by the selection circuit.
8. A microcomputer, comprising:
the pulse-frequency control circuit according to claim 1 ; and
a setter that writes a value to the setting register.
9. A DC-to-DC converter, comprising:
the microcomputer according to claim 8 ;
a switching element that performs switching of an input voltage in accordance with the output pulse sequence provided from the selection circuit, the input voltage being a direct current input voltage;
an energy conversion circuit that, when receiving the input voltage the switching of which has been performed by the switching element, generates an electromotive force due to current fluctuation caused by voltage fluctuation of the input voltage and provides a voltage depending on the electromotive force; and
a rectifying and smoothing circuit that rectifies and smoothes the voltage provided from the energy conversion circuit and provides an output voltage, the output voltage being a direct current output voltage,
wherein the microcomputer further includes a comparator that compares a potential of the output voltage with a predetermined potential, and
the setter performs the writing based on a comparison result by the comparator so that the potential of the output voltage is closer to the predetermined potential.
10. A pulse-frequency control method performed by a pulse-frequency control circuit including a selection circuit, a setting register, and a control circuit, the selection circuit receiving, and selecting from among, a plurality of reference clocks whose phases differ from one another and which have a same reference period, the pulse-frequency control method comprising:
storing, by the setting register, information for identifying a setting period that is in increments of a first duration shorter than the reference period;
causing, by the control circuit, based on the information stored by the storing, the selection circuit to sequentially and repeatedly select, as a determined rising edge, a rising edge occurring at intervals of the setting period from among rising edges of the plurality of reference clocks; and
sequentially and repeatedly generating, by the selection circuit, an output pulse whose rising edge coincides with the determined rising edge selected, to provide an output pulse sequence of the output pulses.