Hybrid scheme for improved performance for P-type and N-type FinFETs
A method includes etching a hybrid substrate to form a recess extending into the hybrid substrate. The hybrid substrate includes a first semiconductor layer having a first surface orientation, a dielectric layer over the first semiconductor layer, and a second semiconductor layer having a second surface orientation different from the first surface orientation. After the etching, a top surface of the first semiconductor layer is exposed to the recess. A spacer is formed on a sidewall of the recess. The spacer contacts a sidewall of the dielectric layer and a sidewall of the second semiconductor layer. An epitaxy is performed to grow an epitaxy semiconductor region from the first semiconductor layer. The spacer is removed.
1. A device comprising:
a bulk semiconductor layer having a first top surface orientation;
a first semiconductor strip and a second semiconductor strip over and connected to the bulk semiconductor layer;
an isolation region between the first semiconductor strip and the second semiconductor strip, the isolation region comprising a protruding portion protruding down from bottom surfaces of the isolation region, with the bottom surfaces being on opposite sides of the protruding portion of the isolation region;
a first source/drain region overlapping the first semiconductor strip, wherein the first source/drain region is a portion of an n-type Fin Field-Effect Transistor (FinFET), and the first source/drain region has a second top surface orientation different from the first top surface orientation; and
a second source/drain region overlapping the second semiconductor strip, wherein the second source/drain region is a portion of a p-type FinFET, and the second source/drain region has the first top surface orientation.
2. The device of claim 1 , wherein the first source/drain region has a (110) top surface orientation, and the second source/drain region has a (100) top surface orientation.
3. The device of claim 1 , wherein the first source/drain region has a (100) R45 top surface orientation, and the second source/drain region has a (100) top surface orientation.
4. The device of claim 1 , wherein the first source/drain region comprises:
an upper portion and a lower portion, wherein the upper portion and the lower portion have different top surface orientations, wherein a joint of the upper portion and the lower portion is higher than a top surface of the isolation region.
5. The device of claim 4 , wherein the lower portion has the first top surface orientation, and the upper portion has a (110) top surface orientation or a (100) R45 top surface orientation.
6. The device of claim 1 , wherein the protruding portion of the isolation region is in middle between the first semiconductor strip and the second semiconductor strip.
7. The device of claim 1 , wherein the protruding portion has equal distances from the first source/drain region and the second source/drain region.
8. The device of claim 1 , wherein the protruding portion of the isolation region has a tapered profile, with lower portions of the protruding portion being narrower than respective upper portions of the isolation region.
9. A device comprising:
an n-type Fin Field-Effect Transistor (FinFET) comprising:
a first semiconductor material forming a first channel of the n-type FinFET; and
a first semiconductor strip overlapped by the first semiconductor material;
a p-type FinFET comprising:
a second semiconductor material forming a second channel of the p-type FinFET, wherein the first semiconductor material and the second semiconductor material have different top surface orientations; and
a second semiconductor strip overlapped by the second semiconductor material; and
a Shallow Trench Isolation (STI) region between and contacting the first semiconductor strip and the second semiconductor strip, wherein the STI region comprises a protruding portion in a middle of the first semiconductor strip and the second semiconductor strip, and the protruding portion extends lower than opposite bottom surfaces of the STI region.
10. The device of claim 9 , wherein the first semiconductor strip and the second semiconductor strip have a same top surface orientation as the second semiconductor material.
11. The device of claim 9 , wherein the first semiconductor strip and the second semiconductor strip have a different top surface orientation than the first semiconductor material.
12. The device of claim 9 , wherein the first semiconductor material comprises an inner portion, and an outer portion encircling the inner portion in a cross-sectional view of the device, wherein the inner portion and the outer portion are formed of different semiconductor materials.
13. The device of claim 12 , wherein the inner portion comprises silicon, and the outer portion comprises silicon carbon.
14. The device of claim 9 , wherein the first semiconductor material and the first semiconductor strip have different surface orientations.
15. The device of claim 9 , wherein the protruding portion of the STI region is elongated and has a lengthwise direction parallel to source-to-drain directions of the n-type FinFET and the p-type FinFET.
16. A device comprising:
an n-type Fin Field-Effect Transistor (FinFET) comprising:
a first semiconductor strip;
a first semiconductor fin overlapping the first semiconductor strip; and
a first gate stack overlying a portion of the first semiconductor fin;
a p-type FinFET comprising:
a second semiconductor strip;
a second semiconductor fin overlapping the second semiconductor strip; and
a second gate stack overlying a portion of the second semiconductor fin; and
a Shallow Trench Isolation (STI) region between the first semiconductor strip and the second semiconductor strip, wherein the STI region comprises a protruding portion protruding downward from a bulk portion of the STI region, and in a top view of the device, the protruding portion has a lengthwise direction parallel to lengthwise directions of the first semiconductor strip and the second semiconductor strip.
17. The device of claim 16 , wherein the first semiconductor strip and the second semiconductor strip have a same top surface orientation as the second semiconductor fin, and the first semiconductor strip and the second semiconductor strip have a different top surface orientation than the first semiconductor fin.
18. The device of claim 16 , wherein the protruding portion protrudes from a bottom surface of the bulk portion for a depth in a range between about 5 nm and about 40 nm.
19. The device of claim 16 , wherein the first semiconductor strip and the first semiconductor fin have different surface orientations.
20. The device of claim 19 , wherein the first semiconductor strip and the first semiconductor fin that have different surface orientations are in contact with each other.