Fabricating method of oxide layer within peripheral circuit region
A method of changing a formation rate of silicon oxide includes providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines. Later, a cleaning process is performed to clean the substrate and the conductive lines using diluted hydrofluoric acid. After the cleaning process, a silicon oxide layer is formed to cover a sidewall and a bottom of the recess, wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
1. A fabricating method of an oxide layer within a peripheral region, comprising:
providing a substrate divided into a memory cell region and a peripheral circuit region, wherein a plurality of conductive lines are disposed in the memory cell region, the conductive lines are adjacent to one another, a recess is disposed between the conductive lines adjacent to each other, an aspect ratio of the recess is between 10 and 12, and a gate structure is disposed within the peripheral circuit region;
performing a first implantation process to form a lightly doped region in the substrate at two sides of the gate structure, respectively;
after the first implantation process, performing a cleaning process to clean the memory cell region and the peripheral circuit region using diluted hydrofluoric acid; and
after the cleaning process, forming an oxide layer to cover the memory cell region, the peripheral circuit region, the conductive lines and the gate structure.
2. The fabricating method of an oxide layer within a peripheral region of claim 1 , further comprising:
removing the oxide layer in the memory cell region.
3. The fabricating method of an oxide layer within a peripheral region of claim 2 , further comprising:
after removing the oxide layer in the memory cell region, removing part of the oxide layer on the gate structure to form a spacer; and
performing a second implantation process to form a source/drain doped region in the substrate at two sides of the gate structure, respectively, by taking the gate structure and the spacer as a mask.
4. The fabricating method of an oxide layer within a peripheral region of claim 1 , wherein after forming the oxide layer, the oxide layer entirely fills up the recess, and there is no void in the oxide layer.
5. The fabricating method of an oxide layer within a peripheral region of claim 1 , wherein when forming the oxide layer to cover the conductive lines, the oxide layer covers the recess as well, and a formation rate of the oxide layer at a bottom of the recess is greater than a formation rate of the oxide layer at a sidewall of the recess.
6. The fabricating method of an oxide layer within a peripheral region of claim 5 , further comprising:
before the cleaning process, forming a silicon nitride layer to cover the bottom and the sidewall of the recess.
7. The fabricating method of an oxide layer within a peripheral region of claim 2 , wherein the step of removing the oxide layer in the memory cell region comprises using a mixture of hydrofluoric acid and ammonium fluoride to remove the oxide layer in the memory cell region.
8. The fabricating method of an oxide layer within a peripheral region of claim 1 , wherein the oxide layer is silicon oxide.
9. The fabricating method of an oxide layer within a peripheral region of claim 1 , wherein the oxide layer is formed by an atomic layer deposition, a chemical vapor deposition or a physical vapor deposition.
10. A method of changing a formation rate of silicon oxide, comprising:
providing a substrate, wherein two conductive lines are disposed on the substrate and a recess is between the conductive lines;
performing a cleaning process to clean the substrate and the conductive lines using diluted hydrofluoric acid; and
after the cleaning process, forming a silicon oxide layer to cover a sidewall and a bottom of the recess; wherein a formation rate of the silicon oxide layer at the bottom of the recess is greater than a formation rate of the silicon oxide layer at the sidewall of the recess.
11. The method of changing a formation rate of silicon oxide of claim 10 , further comprising:
before the cleaning process, forming a silicon nitride layer to cover the bottom and the sidewall of the recess.
12. The method of changing a formation rate of silicon oxide of claim 11 , wherein the formation rate of the silicon oxide layer on the silicon nitride layer at the bottom of the recess is greater than the formation rate of the silicon oxide layer on the silicon nitride layer at the sidewall of the recess.
13. The method of changing a formation rate of silicon oxide of claim 10 , wherein the silicon oxide layer fills up the recess entirely.