Accelerator for matrix decomposition
Systems and methods for a hardware accelerated matrix decomposition matrix decomposition circuit are described herein. This matrix decomposition circuit splits matrix decomposition operations into parallel operation circuits and serial operation circuits, and joins the parallel and serial operation circuits using specific dependency handling logic for efficient parallel execution. This provides fast matrix decomposition with low power consumption, reduced memory footprint, and reduced memory bandwidth.
1. A hardware accelerated system comprising:
a parallel compute circuit including a first multiply and accumulate (MAC) circuit to obtain a parallel computing input and calculate a parallel MAC single matrix column output based on the parallel computing input and a first matrix column input;
a computation separation circuit to provide a serial computing input based on the parallel MAC single matrix column output;
a serial compute circuit to obtain the serial computing input and calculate a serial computation output;
a decomposition control circuit to calculate a matrix decomposition control; and
a memory access control circuit to calculate the parallel computing input based on the matrix decomposition control.
2. The system of claim 1 , wherein:
the first matrix column input is received at the memory access control circuit from a memory circuit; and
the parallel MAC single matrix column output is stored in a first row buffer.
3. The system of claim 2 , wherein the serial computation output is stored in-place in the memory circuit.
4. The system of claim 2 , wherein:
the first matrix column input is read from the memory circuit in a triangular storage format; and
the serial computation output is stored in the memory circuit in a compressed linear storage format.
5. The system of claim 2 , wherein the parallel compute circuit further includes a second MAC circuit to:
obtain a second matrix column input; and
calculate a parallel MAC dual matrix column output based on the second matrix column input.
6. The system of claim 5 , wherein the second matrix column input is received from the memory circuit at a second row buffer.
7. The system of claim 5 , wherein the computation separation circuit is further to:
obtain the parallel MAC dual matrix column output; and
identify an active parallel MAC output based on the parallel MAC single matrix column output and the parallel MAC dual matrix column output;
wherein the computation separation circuit calculating the serial computing input is further based on the active parallel MAC output and the parallel MAC dual matrix column output.
8. The system of claim 7 wherein:
the parallel compute circuit is further includes a third MAC circuit to obtain a third matrix column input and calculate a parallel MAC multiple matrix column output based on the third matrix column input; and
the computation separation circuit identifying the active parallel MAC output is further based on the parallel MAC multiple matrix column output.
9. The system of claim 1 , wherein the decomposition control circuit is further to obtain a matrix decomposition configuration input, wherein the matrix decomposition control is calculated based on the matrix decomposition configuration input.
10. The system of claim 1 , wherein:
the computation separation circuit is further to calculate a dependency clear control based on the parallel MAC single matrix column output; and
wherein calculation of the serial computing input is further based on the dependency clear control.
11. The system of claim 1 , wherein:
the serial compute circuit includes a serial subtraction circuit to obtain the serial computing input and calculate a serial subtraction output; and
the serial computation output is based on the serial subtraction output.
12. The system of claim 11 , herein the serial compute circuit further includes a square root circuit to:
obtain the serial subtraction output; and
calculate a serial square root output based on the serial subtraction output;
wherein calculation of the serial computation output is further based on the serial square root output.
13. The system of claim 11 , wherein the serial compute circuit further includes an inverse circuit to:
obtain the serial subtraction output; and
calculate a serial inverse output based on the serial subtraction output;
wherein the calculation of the serial computation output is further based on the serial inverse output.
14. The system of claim 11 wherein the memory access control circuit is further to:
obtain the serial subtraction output; and
write the serial subtraction output to a memory.
15. A method comprising:
obtaining a parallel computing input at a parallel compute circuit;
calculating a parallel MAC single matrix column output at a first multiply and accumulate (MAC) circuit within the parallel compute circuit, wherein the parallel MAC single matrix column output is calculated based on the parallel computing input and a first matrix column input;
invoking a computation separation circuit to provide a serial computing input to a serial compute circuit based on the parallel MAC single matrix column output;
providing a serial computation output calculated by the serial compute circuit based on the serial computing input to a memory access control circuit;
calculating a matrix decomposition control at a decomposition control circuit; and
calculating the parallel computing input at the memory access control circuit based on the matrix decomposition control.
16. The method of claim 15 , further including:
obtaining the first matrix column input at the memory access control circuit from a memory circuit; and
storing the parallel MAC single matrix column output in a first row buffer.
17. The method of claim 16 , further including storing the serial computation output in-place in the memory circuit.
18. The method of claim 16 , further including:
reading the first matrix column input from the memory circuit in a triangular storage format; and
storing the serial computation output in the memory circuit in a compressed linear storage format.
19. The method of claim 15 , further including obtaining a matrix decomposition configuration input at the decomposition control circuit, wherein the matrix decomposition control is calculated based on the matrix decomposition configuration input.
20. The method of claim 15 , wherein the computation separation circuit further calculates a dependency clear control based on the parallel MAC single matrix column output, wherein calculating the serial computing input is further based on the dependency clear control.
21. The method of claim 15 , further including calculating a parallel MAC dual matrix column output at a second MAC circuit within the parallel compute circuit based on a second matrix column input.