Semiconductor module for a power conversion circuit for reliably reducing a voltage surge
A semiconductor module according to one embodiment includes a circuit substrate and first and second transistors for upper and lower arms of a power conversion circuit. The circuit substrate includes a substrate having first and second insulating parts and a conductive layer disposed therebetween, first and second input interconnection patterns coupled to the first and second input terminals, and an output interconnection pattern coupled to an output terminal. The first and second transistors are electrically coupled to the first and second input terminals through the first and second input interconnection patterns, respectively. The conductive layer has a first area situated opposite the first input interconnection pattern and a second area electrically coupled to the first area. The second area is electrically coupled to the second input interconnection pattern. The conductive layer is insulated from the first input interconnection pattern and the output interconnection pattern by the second insulating part.
1. A semiconductor module including a power conversion circuit, comprising:
a circuit substrate;
a first transistor mounted on the circuit substrate and constituting an upper arm of the power conversion circuit; and
a second transistor, mounted on the circuit substrate, constituting a lower arm of the power conversion circuit and electrically series-coupled to the first transistor,
wherein the circuit substrate includes:
a substrate having a first insulating part, a second insulating part disposed over the first insulating part, and a conductive layer situated between the first insulating part and the second insulating part;
a first input interconnection pattern disposed on the second insulating part and electrically coupled to a first input terminal through which a first power is supplied to the power conversion circuit, the first input interconnection pattern having the first transistor mounted thereon;
a second input interconnection pattern disposed on the second insulating part and electrically coupled to a second input terminal through which a second power lower than the first power is supplied to the power conversion circuit; and
an output interconnection pattern disposed on the second insulating part and coupled to an output terminal through which an output power of the power conversion circuit is output, the output interconnection pattern having the second transistor mounted thereon,
wherein the first transistor is electrically coupled to the first input interconnection pattern such as to receive the first power through the first input interconnection pattern,
wherein the second transistor is electrically coupled to the second input interconnection pattern such as to receive the second power through the second input interconnection pattern,
wherein the conductive layer includes:
a first area; and
a second area electrically coupled to the first area,
wherein the first area is situated opposite the first input interconnection pattern,
wherein the second area is electrically coupled to the second input interconnection pattern, and
wherein the conductive layer is insulated from the first input interconnection pattern and the output interconnection pattern by the second insulating part.
2. The semiconductor module as claimed in claim 1 , wherein part of the output interconnection pattern is situated between the first input interconnection pattern and the second input interconnection pattern.
3. The semiconductor module as claimed in claim 2 , wherein the conductive layer does not overlap the output interconnection pattern as viewed in a thickness direction of the substrate.
4. The semiconductor module as claimed in claim 3 , wherein the circuit substrate includes an auxiliary interconnection pattern disposed in proximity to the first input interconnection pattern on the second insulating part,
wherein the conductive layer is electrically coupled to the auxiliary interconnection pattern, and
wherein the auxiliary interconnection pattern and the first input interconnection pattern are coupled through a surge voltage absorbing element.
5. The semiconductor module as claimed in claim 4 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
6. The semiconductor module as claimed in claim 3 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
7. The semiconductor module as claimed in claim 2 , wherein the circuit substrate includes an auxiliary interconnection pattern disposed in proximity to the first input interconnection pattern on the second insulating part,
wherein the conductive layer is electrically coupled to the auxiliary interconnection pattern, and
wherein the auxiliary interconnection pattern and the first input interconnection pattern are coupled through a surge voltage absorbing element.
8. The semiconductor module as claimed in claim 7 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
9. The semiconductor module as claimed in claim 2 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
10. The semiconductor module as claimed in claim 1 , wherein the conductive layer does not overlap the output interconnection pattern as viewed in a thickness direction of the substrate.
11. The semiconductor module as claimed in claim 10 , wherein the circuit substrate includes an auxiliary interconnection pattern disposed in proximity to the first input interconnection pattern on the second insulating part,
wherein the conductive layer is electrically coupled to the auxiliary interconnection pattern, and
wherein the auxiliary interconnection pattern and the first input interconnection pattern are coupled through a surge voltage absorbing element.
12. The semiconductor module as claimed in claim 11 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
13. The semiconductor module as claimed in claim 10 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
14. The semiconductor module as claimed in claim 1 , wherein the circuit substrate includes an auxiliary interconnection pattern disposed in proximity to the first input interconnection pattern on the second insulating part,
wherein the conductive layer is electrically coupled to the auxiliary interconnection pattern, and
wherein the auxiliary interconnection pattern and the first input interconnection pattern are coupled through a surge voltage absorbing element.
15. The semiconductor module as claimed in claim 14 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.
16. The semiconductor module as claimed in claim 1 , comprising:
a plurality of said first transistors; and
a plurality of said second transistors,
wherein the plurality of first transistors are mounted on the first input interconnection pattern, and are electrically coupled in parallel, and
wherein the plurality of second transistors are mounted on the output interconnection pattern, and are electrically coupled in parallel.