Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a core member having a through-hole;

a semiconductor chip disposed in the through-hole of the core member and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least a portion of the semiconductor chip;

a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;

a passivation layer disposed on the connection member; and

electrical connection structures disposed on the passivation layer opposite to the connection member,

wherein the fan-out semiconductor package has a first slot spaced apart from the through-hole and penetrating through at least a portion of the core member, and a second slot entirely penetrating through at least a portion of the passivation layer in a thickness direction, and

wherein the second slot is disposed spaced apart from the electrical connection structures.

2. The fan-out semiconductor package of claim 1 , wherein

the first slot is entirely filled with the encapsulant.

3. The fan-out semiconductor package of claim 2 , wherein the first slot is disposed outside a periphery of the through-hole.

4. The fan-out semiconductor package of claim 1 , wherein the first slot is filled with a metal material.

5. The fan-out semiconductor package of claim 1 , wherein

the second slot is externally opened through a surface of the passivation layer facing away from the connection member.

6. The fan-out semiconductor package of claim 5 ,

wherein the second slot is disposed between the electrical connection structures.

7. The fan-out semiconductor package of claim 5 , wherein a portion of the connection member is externally exposed through the second slot.

8. The fan-out semiconductor package of claim 1 , wherein the first slot and the second slot have a rectangular shape, a cross shape, or a line shape on a plane, respectively.

9. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, a first wiring layer in contact with the connection member and embedded in the first insulating layer, and a second wiring layer disposed on a first surface of the first insulating layer opposing a second surface of the first insulating layer in which the first wiring layer is embedded, and

the first and second wiring layers are electrically connected to the connection pads of the semiconductor chip.

10. The fan-out semiconductor package of claim 9 , wherein the core member further includes a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer, and

the third wiring layer is electrically connected to the connection pads of the semiconductor chip.

11. The fan-out semiconductor package of claim 10 , wherein the first slot penetrates through at least portions of the first and second insulating layers from an upper surface of the second insulating layer.

12. The fan-out semiconductor package of claim 1 , wherein the core member includes a first insulating layer, and a first wiring layer and a second wiring layer disposed on opposite surfaces of the first insulating layer, and

the first and second wiring layers are electrically connected to the connection pads of the semiconductor chip.

13. The fan-out semiconductor package of claim 12 , wherein the core member further includes second and third insulating layers disposed on the opposite surfaces of the first insulating layer and covering the first and second wiring layers, and third and fourth wiring layers disposed on the second and third insulating layers, and

the third and fourth wiring layers are electrically connected to the connection pads of the semiconductor chip.

14. The fan-out semiconductor package of claim 13 , wherein the first slot penetrates through at least portions of the first, second, and third insulating layers from an upper surface of the third insulating layer.

15. A fan-out semiconductor package comprising:

a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;

an encapsulant encapsulating at least a portion of the semiconductor chip;

a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip;

a passivation layer disposed on the connection member; and

electrical connection structures disposed on the passivation layer opposite to the connection member,

wherein the fan-out semiconductor package has a second slot entirely penetrating through at least a portion of the passivation layer in a thickness direction, and

wherein the second slot is disposed spaced apart from the electrical connection structures.

16. The fan-out semiconductor package of claim 15 , further comprising:

a core member having a through-hole; and

a first slot of the core member,

wherein the first slot is filled with a material different from a material of the core member, and

the second slot is filled with a material different from a material of the passivation layer.

17. A fan-out semiconductor package comprising:

a connection member including a plurality of insulating layers, and a plurality of redistribution layers each including conductive traces disposed on insulating layers of the plurality of insulating layers;

a core member disposed on a first surface of the connection member;

a semiconductor chip disposed on the first surface of the connection member in a through-hole of the core member, the semiconductor chip having connection pads electrically connected to the redistribution layers of the connection member; and

a passivation layer disposed on a second surface of the connection member opposite to the first surface thereof,

wherein a first slot is disposed in the core member and a second slot is disposed in the passivation layer and the first slot is entirely filled with a material different from that of the core member, and

wherein a portion of the connection member is externally exposed through the second slot.

18. The fan-out semiconductor package of claim 17 , further comprising an encapsulant disposed in the through-hole of the core member and encapsulating at least portions of the core member and the semiconductor chip,

wherein the first slot is entirely filled with the encapsulant.

19. The fan-out semiconductor package of claim 17 , wherein the first slot comprises a plurality of slots each disposed in the core member to be spaced apart from the through-hole between the through-hole and an outer periphery of the core member, each extending through an entire thickness of the core member, and each entirely and homogeneously filled with the material different from that of the core member.

20. The fan-out semiconductor package of claim 19 , wherein the core member comprises first and second insulating layers in contact with each other, and a wiring layer disposed between the first and second insulating layers and electrically connected to the connection pads of the semiconductor chip via the conductive traces of the connection member,

wherein the wiring layer is spaced apart from the through-hole and the slots of the plurality of slots.