Fixed frequency DC-DC converter
In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.
1. A circuit, comprising:
a pulse width modulation (PWM) logic circuit configured to generate a first PWM signal associated with a power switch, the first PWM signal having a first pulse, and a second PWM signal having a second pulse corresponding to and partially overlapping in time with the first pulse, the second pulse having an earlier rising edge and a longer duty cycle than the first pulse of the first PWM signal;
a loop circuit coupled to the PWM logic circuit, and configured to generate a ramp signal based on the second PWM signal; and
a comparator circuit coupled to the loop circuit, and configured to generate a feedback control signal based on the ramp signal, the feedback control signal received by the PWM logic circuit to control a pulse width of the first PWM signal.
2. The circuit of claim 1 , wherein the PWM logic circuit includes:
a set-reset (SR) latch having a reset input coupled to receive the feedback control signal, a set input coupled to receive a clock signal from an oscillator, and a latch output;
a delay element having an input coupled to the latch output, and a delay output;
an AND gate having a first input coupled to the delay output of the delay element, a second input coupled to the latch output, and an AND output;
a first PWM output coupled to the AND output, and configured to output the first PWM signal; and
a second PWM output coupled to the latch output, and configured to output the second PWM signal.
3. The circuit of claim 2 , wherein the delay element includes a rising edge delay buffer.
4. The circuit of claim 1 , wherein:
the first PWM signal has a first rising edge; and
the second PWM signal has a second rising edge leading the first rising edge by a time period approximating a response time of the comparator circuit.
5. The circuit of claim 1 , wherein:
the first PWM signal has a first duty cycle; and
the second PWM signal has a second duty cycle greater than the first duty cycle by a time period approximating a response time of the comparator circuit.
6. The circuit of claim 1 , wherein:
the first PWM signal has a first rising edge; and
the second PWM signal has a second rising edge leading the first rising edge by 80 ns.
7. The circuit of claim 1 , wherein:
the first PWM signal has a first duty cycle; and
the second PWM signal has a second duty cycle greater than the first duty cycle by 80 ns.
8. The circuit of claim 1 , wherein:
the first PWM signal has a first falling edge; and
the second PWM signal has a second falling edge synchronous with the first falling edge.
9. The circuit of claim 1 , wherein the first PWM signal is configured to regulate the power switch.
10. The circuit of claim 1 , wherein the first PWM signal is configured to regulate a power transfer from a input voltage source to an output inductor.
11. A circuit, comprising:
a pulse width modulation (PWM) logic circuit having:
a loop comparator input terminal;
a latch coupled to the loop comparator input terminal;
a first PWM output terminal;
a delay element coupled between the latch and the first PWM output terminal; and
a second PWM output terminal coupled to the latch;
a loop circuit having a loop input coupled to the second PWM output terminal, and a loop output; and
a comparator circuit having a comparator input coupled to the loop output, and a comparator output coupled to the loop comparator input terminal of the PWM logic circuit.
12. The circuit of claim 11 , wherein:
the latch includes a set-reset (SR) latch having a reset input coupled to the loop comparator input terminal, a set input coupled to receive a clock signal from an oscillator, and a latch output;
the PWM logic circuit includes an AND gate having a first input coupled to a delay output of the delay element, a second input coupled to the latch output, and an AND output;
the first PWM output terminal is coupled to the AND output; and
the second PWM output terminal coupled to the latch output.
13. The circuit of claim 11 , wherein the delay element includes a rising edge delay buffer.
14. The circuit of claim 11 , wherein the delay element includes delay time constant approximating a response time of the comparator circuit.
15. The circuit of claim 11 , wherein the delay element includes delay time constant of about 80 ns.
16. The circuit of claim 11 , wherein the first PWM output terminal is coupled to an output driver configured to regulate a power switch.
17. The circuit of claim 11 , wherein the first PWM output terminal is coupled to an output driver configured to regulate a power transfer from a input voltage source to an output inductor.
18. A circuit, comprising:
a pulse width modulation (PWM) logic circuit configured to generate a first PWM signal associated with a power switch, and a second PWM signal having an earlier rising edge than the first PWM signal;
a ramp circuit coupled to the PWM logic circuit, and configured to generate a ramp signal based on the second PWM signal;
a slope compensation circuit coupled to the PWM logic circuit, and configured to generate a slope signal based on the second PWM signal; and
a comparator circuit coupled to the ramp circuit and the slope compensation circuit, and configured to generate a feedback control signal based on the ramp signal and the slope signal, the feedback control signal received by the PWM logic circuit to control a pulse width of the first PWM signal.
19. The circuit of claim 18 , wherein:
the first PWM signal has a first rising edge; and
the second PWM signal has a second rising edge leading the first rising edge by a time period approximating a response time of the comparator circuit.
20. The circuit of claim 18 , wherein:
the first PWM signal has a first falling edge; and
the second PWM signal has a second falling edge synchronous with the first falling edge.