High-frequency signal processing apparatus and wireless communication apparatus
A high-frequency signal processing apparatus and a wireless communication apparatus can achieve a decrease in power consumption. For example, when an indicated power level to a high-frequency power amplifier is equal to or greater than a second reference value, envelope tracking is performed by causing a source voltage control circuit to control a high-speed DCDC converter using a detection result of an envelope detecting circuit and causing a bias control circuit to indicate a fixed bias value. The source voltage control circuit and the bias control circuit indicate a source voltage and a bias value decreasing in proportion to a decrease in the indicated power level when the indicated power level is in a range of the second reference value to the first reference value, and indicate a fixed source voltage and a fixed bias value when the indicated power level is less than the first reference value.
1. A wireless communication apparatus comprising:
first and second power amplifying circuits coupled in parallel between an input node and an output node, each of the first and second power amplifying circuits having a transistor;
a source voltage generating circuit;
a bias supply circuit configured to supply a bias to the first and second power amplifying circuits; and
an envelope detecting circuit configured to detect an envelope of an input signal input to the input node,
wherein the source voltage generating circuit is configured to:
supply a first source voltage to a drain or a collector of the transistor of the first power amplifying circuit when the wireless communication apparatus is operating in a first power mode, the first source voltage varying along the envelope detected by the envelope detecting circuit, and
supply a second source voltage to a drain or a collector of the transistor of the second power amplifying circuit when the wireless communication apparatus is operating in a second power mode, the second source voltage varying in proportion to an average power level of an output signal at the output node, and the second power mode being a lower power mode than the first power mode, and
wherein the bias supply circuit is configured to:
as a first operation, supply the bias to a gate or a base of the transistor of the first power amplifying circuit and not supply the bias to a gate or a base of the transistor of the second power amplifying circuit when the wireless communication apparatus is operating in the first power mode, and
as a second operation, supply the bias to the gate or the base of the transistor of the second power amplifying circuit and not supply the bias to the gate or the base of the transistor of the first power amplifying circuit when the wireless communication apparatus is operating in the second power mode.
2. The wireless communication apparatus according to claim 1 , wherein the source voltage generating circuit is further configured to:
generate the first source voltage when an output power control signal indicates that the wireless communication apparatus is operating at a first power level, and
generate the second source voltage when the output power control signal indicates that the wireless communication apparatus is operating at a second power level, the second power level being a higher power level than the first power level.
3. The wireless communication apparatus according to claim 2 , wherein the bias supply circuit is further configured to:
perform the first operation when a power mode control signal indicates that the wireless communication apparatus is operating in the first power mode, and
perform the second operation when the power mode control signal indicates that the wireless communication apparatus is operating in the second power mode.
4. The wireless communication apparatus according to claim 1 , wherein the bias supply circuit is further configured to:
perform the first operation when a power mode control signal indicates that the wireless communication apparatus is operating in the first power mode, and
perform the second operation when the power mode control signal indicates that the wireless communication apparatus is operating in the second power mode.
5. A power amplifier module comprising:
first and second power amplifying circuits coupled in parallel between an input node and an output node, each of the first and second power amplifying circuits having a transistor; and
a bias supply circuit configured to supply a bias to the first and second power amplifying circuits,
wherein the first power amplifying circuit is configured to receive a first source voltage through a drain or a collector of the transistor of the first power amplifying circuit when the power amplifier module is operating in a first power mode, the first source voltage being time variable and correlated with an envelope signal of an input signal at the input node,
wherein the second power amplifying circuit is configured to receive a second source voltage through a drain or a collector of the transistor of the second power amplifying circuit when the power amplifier module is operating in a second power mode, the second source voltage varying in proportion to an average power level of an output signal at the output node, and the second power mode being a lower power mode than the first power mode, and
wherein the bias supply circuit is configured to:
as a first operation, supply the bias to a gate or a base of the transistor of the first power amplifying circuit and not supply the bias to a gate or a base of the transistor of the second power amplifying circuit when the power amplifier module is operating in the first power mode, and
as a second operation, supply the bias to the gate or the base of the transistor of the second power amplifying circuit and not supply the bias to the gate or the base of the transistor of the first power amplifying circuit when the power amplifier module is operating in the second power mode.