IP Library › Granted Patent US 10,551,860
Granted Patent B2
US 10,551,860 · App. 16/258,917 · Granted Feb 4, 2020

Regulator for reducing power consumption

Inventor: Makoto Yasusaka (Kyoto, JP)
Assignee: Rohm Co., Ltd.
G05F1/575G05F1/445G05F1/565H02M3/156
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Quick Facts
Patent No.
US 10,551,860
App. No.
16/258,917
Granted
Feb 4, 2020
Kind
B2
Abstract

There is provided a regulator including: a first transistor connected between an input terminal and an output terminal; a feedback circuit configured to control a control voltage of a control electrode of the first transistor so that a voltage of the output terminal reaches a target voltage according to a feedback voltage proportional to an output voltage; a second transistor having a control electrode to which the control voltage is applied in common with the first transistor; a first resistor connected with the second transistor in series between the input terminal and the output terminal; and a current limiting circuit configured to detect a voltage generated across the first resistor and to change the control voltage so as to limit a current flowing through the first transistor.

Claims (38)

1. A regulator, comprising:

a first transistor connected between an input terminal and an output terminal;

a feedback circuit configured to control a control voltage of a control electrode of the first transistor so that a voltage of the output terminal reaches a target voltage according to a feedback voltage proportional to an output voltage;

a second transistor having a control electrode to which the control voltage is applied in common with the first transistor;

a first resistor connected with the second transistor in series between the input terminal and the output terminal; and

a current limiting circuit including a third transistor having a source connected to a drain of the second transistor, and configured to apply a voltage generated across the first resistor between a gate and the source of the third transistor, and to change the control voltage so as to limit a current flowing through the first transistor when the third transistor is turned on.

2. The regulator of claim 1 , wherein the first transistor and the second transistor are P-channel type field effect transistors whose source electrodes are connected to each other,

and

wherein the third transistor is a P-channel type field effect transistor having a drain connected to gates of the first transistor and the second transistor.

3. The regulator of claim 1 , wherein the first transistor and the second transistor are P-channel type field effect transistors whose source electrodes are connected to each other, and

wherein the third transistor is a P-channel type field effect transistor, and the current limiting circuit includes a circuit configured to increase voltages of gates of the first transistor and the second transistor when the third transistor is turned on.

4. The regulator of claim 1 , wherein the first transistor and the second transistor are P-channel type field effect transistors whose source electrodes are connected to each other, and

wherein the third transistor is a P-channel type field effect transistor, and the current limiting circuit includes a circuit configured to control the feedback circuit so as to increase an output of the feedback circuit when the third transistor is turned on.

5. A regulator, comprising:

a first transistor connected between an input terminal and an output terminal;

a feedback circuit configured to control a control voltage of a control electrode of the first transistor so that a voltage of the output terminal reaches a target voltage according to a feedback voltage proportional to an output voltage;

a second transistor having a control electrode to which the control voltage is applied in common with the first transistor;

a first resistor connected with the second transistor in series between the input terminal and the output terminal; and

a current limiting circuit configured to detect a voltage generated across the first resistor and to change the control voltage so as to limit a current flowing through the first transistor,

wherein the first transistor and the second transistor are P-channel type field effect transistors whose source electrodes are connected to each other,

wherein the current limiting circuit includes a third transistor, and

wherein the third transistor is a P-channel type field effect transistor having a source connected to a drain of the second transistor, and a drain connected to gates of the first transistor and the second transistor, so that the voltage generated across the first resistor is applied between a gate and the source of the third transistor.

6. A regulator, comprising:

a first transistor connected between an input terminal and an output terminal;

a feedback circuit configured to control a control voltage of a control electrode of the first transistor so that a voltage of the output terminal reaches a target voltage according to a feedback voltage proportional to an output voltage;

a second transistor having a control electrode to which the control voltage is applied in common with the first transistor;

a first resistor connected with the second transistor in series between the input terminal and the output terminal; and

a current limiting circuit configured to detect a voltage generated across the first resistor and to change the control voltage so as to limit a current flowing through the first transistor,

wherein the first transistor and the second transistor are P-channel type field effect transistors whose source electrodes are connected to each other, and

wherein the current limiting circuit includes a third transistor as a P-channel type field effect transistor having a source connected to a drain of the second transistor so that the voltage generated across the first resistor is applied between a gate and the source of the third transistor, and a circuit configured to increase voltages of gates of the first transistor and the second transistor when the third transistor is turned on.

7. A regulator, comprising:

a first transistor connected between an input terminal and an output terminal;

a feedback circuit configured to control a control voltage of a control electrode of the first transistor so that a voltage of the output terminal reaches a target voltage according to a feedback voltage proportional to an output voltage;

a second transistor having a control electrode to which the control voltage is applied in common with the first transistor;

a first resistor connected with the second transistor in series between the input terminal and the output terminal; and

a current limiting circuit configured to detect a voltage generated across the first resistor and to change the control voltage so as to limit a current flowing through the first transistor,

wherein the first transistor and the second transistor are P-channel type field effect transistors whose source electrodes are connected to each other, and

wherein the current limiting circuit includes a third transistor as a P-channel type field effect transistor having a source connected to a drain of the second transistor so that the voltage generated across the first resistor is applied between a gate and the source of the third transistor, and a circuit configured to control the feedback circuit so as to increase an output of the feedback circuit when the third transistor is turned on.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2019
From: YASUSAKA, MAKOTO
To: ROHM CO., LTD.
Reel/Frame 048164/0254 →
Priority Claims (1)
JP 2018-012858 · Jan 29, 2018 · national
Continuity (1)
Related Publication 20190235548A1 · Aug 1, 2019
Cited By (1)
US 12,372,992