Semiconductor devices

1. A semiconductor device comprising:

a substrate including a plurality of active patterns;

a device isolation layer filling a trench between a pair of adjacent active patterns of the plurality of active patterns;

a gate electrode on the plurality of active patterns; and

a gate contact on the gate electrode,

wherein each active pattern of the plurality of active patterns includes a separate source/drain pattern, of a plurality of source/drain patterns, at each side of opposite sides of the gate electrode,

wherein the gate contact includes

a first portion vertically overlapping with the gate electrode, a bottom surface of the first portion being a closest surface of the gate contact to the substrate, the bottom surface of the first portion distal from the substrate in relation to the gate electrode; and

a second portion laterally extending from the first portion such that the second portion vertically overlaps with the device isolation layer and does not vertically overlap with the gate electrode,

wherein a bottom surface of the second portion is distal to the substrate in relation to the bottom surface of the first portion,

wherein the bottom surface of the second portion is distal to the substrate in relation to a top of a source/drain pattern of the plurality of source/drain patterns that is adjacent to the second portion,

wherein the semiconductor device further includes an interlayer insulating layer covering the plurality of source/drain patterns,

wherein the plurality of active patterns extend in a first direction,

wherein the gate electrode extends in a second direction, the second direction intersecting the first direction,

wherein the interlayer insulating layer is between source/drain patterns adjacent to each other in the second direction,

wherein the second portion is on the interlayer insulating layer.

2. The semiconductor device of claim 1 , wherein at least a portion of the source/drain pattern that is adjacent to the second portion vertically overlaps with the second portion.

3. The semiconductor device of claim 1 , wherein a bottom surface of the gate contact has a stepped profile at a boundary between the first portion and the second portion.

4. The semiconductor device of claim 1 , wherein a vertical thickness of the second portion is inversely proportional to a horizontal distance from the first portion.

5. The semiconductor device of claim 1 , further comprising:

a via on the second portion; and

a word line electrically connected to the gate contact through the via,

wherein the active patterns and the gate electrode include memory transistors of a static random access memory (SRAM) cell.

6. The semiconductor device of claim 1 , wherein further comprising:

a plurality of gate electrodes on the plurality of active patterns, the plurality of gate electrodes including the gate electrode,

wherein the gate contact is connected in common to adjacent gate electrodes of the plurality of gate electrodes via separate, respective first portions vertically overlapping with the adjacent gate electrodes, and

wherein the second portion of the gate contact is between the first portions.

7. The semiconductor device of claim 6 , wherein the plurality of active patterns include

a first active pattern on a PMOSFET region of the substrate, and

a second active pattern on an NMOSFET region of the substrate,

wherein the gate contact is on the device isolation layer and is between the PMOSFET region and the NMOSFET region.

8. The semiconductor device of claim 1 , further comprising:

a plurality of active contacts on separate, respective source/drain patterns of the plurality of source/drain patterns,

wherein top surfaces of the active contacts are substantially coplanar with a top surface of the gate contact.

9. The semiconductor device of claim 1 , wherein

upper portions of the plurality of active patterns have fin-shapes vertically protruding from the device isolation layer, and

the plurality of source/drain patterns include epitaxial patterns in the upper portions of the plurality of active patterns.

10. A semiconductor device comprising:

a substrate including an active pattern extending in a first direction;

a device isolation layer on the substrate, such that the device isolation layer defines at least one boundary of the active pattern;

a gate electrode on the device isolation layer, the gate electrode intersecting the active pattern, the gate electrode extending in a second direction; and

a gate contact on the gate electrode,

wherein the active pattern includes a source/drain pattern at one side of the gate electrode,

wherein the gate contact includes

a first portion vertically overlapping with the gate electrode, and

a second portion extending from the first portion in the first direction,

wherein a bottom surface of the second portion is distal to the substrate in relation to a bottom surface of the first portion, and

wherein at least a portion of the source/drain pattern vertically overlaps with the second portion,

wherein the semiconductor device further includes an interlayer insulating layer covering the source/drain pattern,

wherein the second portion is isolated from direct contact with the source/drain pattern, and the interlayer insulating layer is between the second portion and the source/drain pattern.

11. The semiconductor device of claim 10 , wherein the bottom surface of the second portion is distal to the substrate in relation to a top of the source/drain pattern.

12. The semiconductor device of claim 10 , further comprising:

a via on the second portion; and

a word line electrically connected to the gate contact through the via,

wherein the active pattern and the gate electrode include an access transistor of a static random access memory (SRAM) cell.

13. The semiconductor device of claim 10 , further comprising:

a plurality of gate electrodes on the active pattern, the plurality of gate electrodes including the gate electrode,

wherein the gate contact is connected in common to adjacent gate electrodes of the plurality of gate electrodes via separate, respective first portions vertically overlapping with the adjacent gate electrodes, and

wherein the second portion of the gate contact is between the first portions.

14. A semiconductor device comprising:

a static random access memory (SRAM) cell on a substrate,

wherein the SRAM cell includes

first and second access transistors;

first and second pull-up transistors; and

first and second pull-down transistors,

wherein a gate electrode of the first access transistor is electrically connected to a word line through a gate contact and a via on the gate contact,

wherein the gate contact includes

a first portion vertically overlapping with the gate electrode, a bottom surface of the first portion being a closest surface of the gate contact to the substrate, the bottom surface of the first portion distal from the substrate in relation to the gate electrode, and

a second portion laterally extending from the first portion,

wherein the via is on the second portion, and

wherein a bottom surface of the second portion is distal to the substrate in relation to the bottom surface of the first portion.

15. The semiconductor device of claim 14 , wherein

a source/drain pattern of the first access transistor is adjacent to the second portion, and

the bottom surface of the second portion is distal to the substrate in relation to a top of the source/drain pattern.

16. The semiconductor device of claim 15 , wherein at least a portion of the source/drain pattern vertically overlaps with the second portion.

17. The semiconductor device of claim 16 , further comprising:

an interlayer insulating layer covering the source/drain pattern,

wherein the second portion is isolated from direct contact with the source/drain pattern, and the interlayer insulating layer is between the second portion and the source/drain pattern.

18. The semiconductor device of claim 14 , wherein the first and second access transistors, first and second pull-up transistors, and first and second pull-down transistors of the SRAM cell have active patterns, which have fin-shapes vertically protruding from a device isolation layer, as active regions.