Three-dimensional semiconductor memory devices

1. A three-dimensional semiconductor memory device comprising:

an electrode structure including a plurality of gate electrodes stacked in a first direction that is perpendicular to a top surface of a substrate;

a lower pattern group including a plurality of lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate;

an upper pattern group including a plurality of upper vertical patterns that are in an upper portion of the electrode structure, wherein the plurality of upper vertical patterns are connected to the plurality of lower vertical patterns, respectively; and

two common source plugs spaced apart from each other in a second direction that is parallel to the top surface of the substrate, wherein the electrode structure is between the two common source plugs,

wherein an upper portion of the lower pattern group has a first width in the second direction, an upper portion of the upper pattern group has a second width in the second direction, and the first width is greater than the second width.

2. The device of claim 1 , wherein the electrode structure comprises opposing sides that are spaced apart from each other in the second direction, and

wherein the opposing sides of the electrode structure are sloped relative to the top surface of the substrate, and a width of a top end of the electrode structure is less than a width of a bottom end of the electrode structure.

3. The device of claim 1 , wherein each of the plurality of lower vertical patterns comprises:

one of a plurality of lower vertical channels, wherein the plurality of lower vertical channels are in the lower portion of the electrode structure and are connected to the substrate; and

one of a plurality of lower conductive pads, wherein the plurality of lower conductive pads are on the plurality of lower vertical channels, respectively, and

wherein the plurality of upper vertical patterns are connected to the plurality of lower conductive pads, respectively.

4. The device of claim 3 , wherein each of the plurality of upper vertical patterns comprises:

one of a plurality of upper vertical channels, wherein the plurality of upper vertical channels are in the upper portion of the electrode structure and are connected to the plurality of lower conductive pads, respectively; and

one of a plurality of upper conductive pads, wherein the plurality of upper conductive pads are on the plurality of upper vertical channels, respectively.

5. The device of claim 4 , further comprising a plurality of bit lines on the electrode structure, wherein the plurality of bit lines are spaced apart from each other, and

wherein the plurality of upper vertical patterns are connected to the plurality of bit lines, respectively, through a respective one of the plurality of upper conductive pads.

6. The device of claim 1 , further comprising two common source regions in the substrate and spaced apart from each other in the second direction, wherein the electrode structure is between the two common source regions, and

wherein the two common source plugs are connected to the two common source regions, respectively.

7. The device of claim 1 , wherein a width of an upper portion of one of the plurality of lower vertical patterns is greater than a width of an upper portion of one of the plurality of upper vertical patterns.

8. The device of claim 1 , wherein the upper pattern group comprises an upper sub-group including a group of the plurality of upper vertical patterns arranged in a zigzag fashion along the second direction,

wherein a pair of directly adjacent ones of the plurality of upper vertical patterns in the upper sub-group are spaced apart from each other by a first distance,

wherein the lower pattern group comprises a lower sub-group including a group of the plurality of lower vertical patterns arranged in a zigzag fashion along the second direction, and

wherein a pair of directly adjacent ones of the plurality of lower vertical patterns in the lower sub-group are spaced apart from each other by a second distance that is greater than the first distance.

9. The device of claim 8 , wherein the group of the plurality of lower vertical patterns comprises a first lower vertical pattern, a second lower vertical pattern that is directly adjacent to the first lower vertical pattern, and a third lower vertical pattern directly adjacent to the second lower vertical pattern,

wherein the second lower vertical pattern is between the first lower vertical pattern and the third lower vertical pattern, and one of the two common source plugs is closer to the third lower vertical pattern than the first lower vertical pattern,

wherein the first lower vertical pattern and the second lower vertical pattern are spaced apart from each other by a third distance, the second lower vertical pattern and the third lower vertical pattern are spaced apart from each other by a fourth distance, and the third distance is less than the fourth distance.

10. The device of claim 1 , wherein the plurality of lower vertical patterns comprise an outermost lower vertical pattern that is closest to one of the two common source plugs, and the plurality of upper vertical patterns comprise an outermost upper vertical pattern that is closest to the one of the two common source plugs,

wherein a midpoint of an upper surface of the outermost lower vertical pattern is offset from a midpoint of a lower surface of the outermost upper vertical pattern by a first distance toward the one of the two common source plugs.

11. The device of claim 10 , wherein the plurality of lower vertical patterns further comprise a second outermost lower vertical pattern that is closest to the outermost lower vertical pattern and is spaced apart from the outermost lower vertical pattern in the second direction, and the plurality of upper vertical patterns further comprises a second outermost upper vertical pattern that is closest to the outermost upper vertical pattern and is spaced apart from the outermost upper vertical pattern in the second direction,

wherein a midpoint of an upper surface of the second outermost lower vertical pattern is offset from a midpoint of a lower surface of the second outermost upper vertical pattern by a second distance toward the one of the two common source plugs, and

wherein the first distance is greater than the second distance.

12. A three-dimensional semiconductor memory device, comprising:

a substrate including a first region and a second region;

an electrode structure on the first region of the substrate and including a plurality of gate electrodes stacked in a first direction that is perpendicular to a top surface of the substrate;

an electrode pad structure extending from the electrode structure toward the second region of the substrate and including a plurality of electrode pads respectively extending from the plurality of gate electrodes, the plurality of electrode pads forming a stepwise structure on the second region;

a lower dummy group including a plurality of lower dummy structures that are in a lower portion of the electrode pad structure and are connected to the substrate;

an upper dummy group including a plurality of upper dummy structures that are in an upper portion of the electrode pad structure, the lower dummy group being between the substrate and the upper dummy group; and

two common source plugs spaced apart from each other in a second direction, the electrode pad structure being between the two common source plugs, and the second direction being parallel to the top surface of the substrate,

wherein an upper portion of the lower dummy group has a first width in the second direction, an upper portion of the upper dummy group has a second width in the second direction, and the first width is greater than the second width.

13. The device of claim 12 , further comprising a plurality of first pad contact plugs connected to the plurality of electrode pads, respectively,

wherein the plurality of upper dummy structures surround one of the plurality of first pad contact plugs.

14. The device of claim 12 , wherein the electrode pad structure comprises opposing sides that are spaced apart from each other in the second direction, and

wherein the opposing sides of the electrode pad structure are sloped relative to the top surface of the substrate, and a width of a top end of the electrode pad structure is less than a width of a bottom end of the electrode pad structure.

15. The device of claim 12 , wherein an upper portion of one of the plurality of lower dummy structures has a third width, an upper portion of one of the plurality of upper dummy structures has a fourth width, and the third width is greater than the fourth width.

16. The device of claim 12 , wherein a number of the plurality of lower dummy structures is greater than a number of the plurality of upper dummy structures.

17. The device of claim 12 , further comprising:

a lower pattern group including a plurality of lower vertical patterns that are in a lower portion of the electrode structure and are connected to the substrate; and

an upper pattern group including a plurality of upper vertical patterns that are in an upper portion of the electrode structure and are connected to the plurality of lower vertical patterns, respectively,

wherein the plurality of lower dummy structures comprise the same material as the plurality of lower vertical patterns, and

wherein the plurality of upper dummy structures comprise the same material as the plurality of upper vertical patterns.

18. The device of claim 17 , wherein each of the plurality of lower dummy structures and the plurality of lower vertical patterns comprises:

a lower vertical channel extending in the first direction from the substrate; and

a lower conductive pad on the lower vertical channel,

wherein the plurality of upper vertical patterns are connected to a plurality of lower conductive pads, respectively.

19. The device of claim 18 , wherein each of the plurality of upper dummy structures and the plurality of upper vertical patterns comprises:

an upper vertical channel extending in the first direction; and

an upper conductive pad on the upper vertical channel.

20. The device of claim 12 , wherein the plurality of upper dummy structures are connected to the plurality of lower dummy structures, respectively.